You will design a custom Application Speci c Integrated Circuit (ASIC) implementation of an N x N array multiplier. The ASIC will be fabricated in AMI 0.5m CMOS technology available through MOSIS.

2 Background and Requirements You already know how to multiply two binary numbers. Figure 11 shows an example of multiplica- tion of two unsigned 6-bit numbers. The first number (1210) is the multiplicand and second number (510) is the multiplier. Six partial products (rows) are generated which when summed column wise yields the product (6010) 1100 121 0101 5 1100 Multiplicand Multiplier 1 Partial Products 1100 00111100:60 Product 10 FIG 10.67 Multiplication example Figure 1: Binary Multiplication - An Example If the multiplicand is represented by Y = { yM-1, yM-2, , yl, ), and multiplier as X = N-1,2N-2,... ,21, o , then the product, P, is given by Equation 1. The inner summation results in partial products while the outer one sums the partial products. This can be depicted as in Figure 2, Note that M = N in this project Note the figures are from Weste and Harris, 3rd edition. 2 Background and Requirements You already know how to multiply two binary numbers. Figure 11 shows an example of multiplica- tion of two unsigned 6-bit numbers. The first number (1210) is the multiplicand and second number (510) is the multiplier. Six partial products (rows) are generated which when summed column wise yields the product (6010) 1100 121 0101 5 1100 Multiplicand Multiplier 1 Partial Products 1100 00111100:60 Product 10 FIG 10.67 Multiplication example Figure 1: Binary Multiplication - An Example If the multiplicand is represented by Y = { yM-1, yM-2, , yl, ), and multiplier as X = N-1,2N-2,... ,21, o , then the product, P, is given by Equation 1. The inner summation results in partial products while the outer one sums the partial products. This can be depicted as in Figure 2, Note that M = N in this project Note the figures are from Weste and Harris, 3rd edition