Your are designing a direct$-$mapped cache with the following specifications:

$-$ Cache size: $65536$ bytes

$-$ Block size: $128$ bytes

$-$ Memory address: $32$ bits

a$)$ Number of cache blocks $=$

b$)$ Number of offset bits $=$

c$)$ Number of index bits $=$

d$)$ Number of tag bits $=$

For the memory address $0$x$55667788$

e$)$ Tag value $($in binary$)$

f$)$ Index value $($in binary$)$

g$)$ Offset value $($in binary$)$