Question: Your circuit has an unexpected state transition when Y = 0 and clock does a full cycle, producing an output Z = 1 when there

Your circuit has an unexpected state transition when Y =0 and clock does a full cycle, producing an output Z =1 when there shouldn't be.
How to fix this? Please make it visual and tell me exactly what to do in the simplest way possible.
Your circuit has an unexpected state transition

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