Your task is to decide whether a particular instruction should be added or not to the ISA of a CPU microarchitecture with the goal of better supporting memory access heavy media streaming applications. The ISA currently supports the following mix of instructions whose execution frequencies are given for two types of benchmarks:

Instruction Type	Latency in cycles	Generic Benchmark Inst. Execution Freq.	Media Bench. Inst. Execution Freq.
Load/Store	5 cycles	25 %	45 %
Register Type	2 cycle	55 %	30 %
Conditional Branch	3 cycles	15 %	15 %
Jump	2 cycles	5 %	10 %

Compute the average CPI for the current architecture for both benchmarks.

Assume that you are given an opportunity of reduce the CPI for the multimedia benchmark by introducing a new adder to resolve memory address computations faster. The new adder reduces the load/store type latencies to 4 cycles. The side effect of integrating a new adder into the datapath is that the processor can run at most at a 20% reduced clock frequency. Compare the performance of the new architecture to the original for both benchmarks.