Your task is to design a memory module built out of eight 64M X 8 DRAMS. (In other words, you'll use eight DRAMS; each DRAM contains 64M supercells and each supercell is 8 bits.) How many bytes of data will the memory module return to the memory controller after a read?

Your task is to design a memory module built out of eight 64M X 8 DRAMS. (In other words, you'll use eight DRAMS; each DRAM contains 64M supercells and each supercell is 8 bits.) How many bits are needed to store an address?

Your task is to design a memory module built out of eight 64M X 8 DRAMS. (In other words, you'll use eight DRAMS; each DRAM contains 64M supercells and each supercell is 8 bits.) What is the total size of the memory in bytes

Your task is to design a memory module built out of sixteen 128M X 8 DRAMS. (In other words, you'll use sixteen DRAMS; each DRAM contains 128M supercells and each supercell is 8 bits.) How many bytes of data will the memory module return to the memory controller after a read?

Your task is to design a memory module built out of sixteen 128M X 8 DRAMS. (In other words, you'll use sixteen DRAMS; each DRAM contains 128M supercells and each supercell is 8 bits.) How many bits are needed to store an address?

Your task is to design a memory module built out of sixteen 128M X 8 DRAMS. (In other words, you'll use sixteen DRAMS; each DRAM contains 128M supercells and each supercell is 8 bits.) How many bits of the address are needed to identify the chunk of data returned by the memory module? (This is portion of the address that is used by each DRAM to select the desired byte.)

Your task is to design a memory module built out of sixteen 128M X 8 DRAMS. (In other words, you'll use sixteen DRAMS; each DRAM contains 128M supercells and each supercell is 8 bits.) What is the total size of the memory in bytes?

Your task is to design a memory module built out of sixteen 128M X 8 DRAMS. (In other words, you'll use sixteen DRAMS; each DRAM contains 128M supercells and each supercell is 8 bits.) What are the array dimensions of each DRAM that minimize max(br, bc), the maximum number of bits needed to address the rows or columns of the array? Give your answer in the form (br, bc).