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Computer Architecture $($ECGR $4181/5181)$

Assignment $3$: RISC$-$V Decoder Design $[50$ points$]$

Consider the Decoder of a processor using the von Neumann architecture $($discussed in class$).$

The processor uses a subset of the RISC$-$V ISA $($RV$32$I, RV$32$F and RV$32$M$)$ from the $$p$15$

RISCV Table$$ in Lectures. The double words, ecall, ebreak, fence, and $$cs$$ ops are to be

ignored. We are considering UNPIPELINED design for this assignment.

$1)$ Draw the schematic of the architecture where the different components $($in the fetch,

decode, execute, writeback stages$)$ are shown as black boxes, their ports are clearly

defined, and connections between these ports detailed. Explain the purpose of these

ports and connections. $[30$ points$]$

$2)$ Write the Decoder code $($in C$++)$ and comment in the code to highlight the executions for

every instruction. $[20$ points$]$