Consider the NMOS amplifier with saturated load in Figure 4.39(a). The transistor parameters are \(V_{T N D}=V_{T N L}=0.6 \mathrm{~V}, k_{n}^{\prime}=100 \mu \mathrm{A} / \mathrm{V}^{2}, \lambda=0\), and \((W / L)_{L}=1\). Let \(V_{D D}=3.3 \mathrm{~V}\).

(a) Design the circuit such that the small-signal voltage gain is \(\left|A_{v}\right|=5\) and the \(Q\)-point is in the center of the saturation region.

(b) Determine \(I_{D Q}\) and \(V_{D S D Q}\).

Figure 4.39(a):-

Transcribed Image Text:

Vi +1 VDD + VGSL + ML VDSL O VO + + VGSD MD VDSD + VGS (a)