17. The protocol for a certain data bus is shown in the table below. Draw the corresponding timing diagram. You may refer to Figure 7.11.

Time Salient Bus Signal Meaning t0 Assert Read Bus is needed for reading (not writing)

t1 Assert Address Indicates where bytes will be written t2 Assert Request Request read to address on address lines t3–t7 Data Lines Read data (requires several cycles)

t4 Assert Ready Acknowledges read request, bytes placed on data lines t4 Lower Request Request signal no longer needed t8 Lower Ready Release bus