Question: Fault models and failures Consider again the circuit of Example 5.1. 1. Deterrnine by formal analysis the failures provoked by each fault of the single

Fault models and failures Consider again the circuit of Example 5.1.

1. Deterrnine by formal analysis the failures provoked by each fault of the single stuck at 0/1 model. Draw and compare the resulting truth tables.

2. Make the same analysis with various functional faults transforming the AND and OR gates.

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