The speed of a transistor is directly proportional to the width of its polysilicon gate, with a narrower gate resulting in a faster transistor and a wider gate resulting in a slower transistor. Knowing that the manufacturing process has a certain variation for the gate width, say ±0.1 (m, how might a designer alter the gate size of a critical circuit in order to minimize its speed variation? Are there any penalties for making this change? Explain.