I have over 7 years of experience in teaching and technical mentoring. I spent 2 years at IDRBT in an academic setting, guiding students in electronics and digital systems. Professionally, I’ve worked extensively with Verilog, VHDL, and FPGA-based design. Additionally, I’ve been a subject matter expert on Chegg for the past 5 years, solving complex engineering problems and helping students understand core concepts.
Working on FPGA, System on Chip design in vivado as client comapny AMD
2023 — 2023
Moschip Technologies
Hands-on experience on RTL quality checks in Spyglass
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Worked on Inter-Integrated Circuit protocol for wishbone application
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Worked on Watch Dog Timer, Barrel Shifter, FIFO, SRAM
2022 — 2022
L&t Technology Services
Worked on LInt and CDC using Spyglass
2020 — 2022
Idrbt
Identified three different threat models in existing design obfuscation techniques in HLS level.
• Implemented the obfuscation on standard DSP express HLS benchmarks, namely ARF, BPF, JPEG, MPEG, FFT, MESA, IIRB and FIR Filter designs to target the 15nm Nan Gate standard cell library.
• Implemented an Automatic Test Pattern Generator for security hardware.
• Implemented a password locking mechanism for obfuscating entire HLS flow using FSM.
• Proficient in RTL Verilog coding for digital logic design, synthesis and implementation using altera.
• Worked on Configurable Ring Oscillator and RRO Physical Unclonable Function.
• Gained Knowledge on FPGA Reverse Engineering from the bitstream to RTL conversion.
