What would be the baseline performance (in cycles, per loop iteration) of the code sequence in Figure 2.35 if no new instruction execution could be initiated until the previous instruction execution had completed? Ignore front-end fetch and decode. Assume for now that execution does not stall for lack of the next instruction, but only one instruction/cycle can be issued. Assume the branch is taken, and that there is a 1 cycle branch delay slot.

Figure 2.35 Code and latencies for Exercise 2.1 through 2.6.

Loop: LD F2,0(Rx) I0 MULTD F2, FO, F2 : DIVD F8, F2,FO I2 LD F4,0(Ry) 13 ADDD F4, FO, F4 14 ADDD F10,F8, F2 I5 SD F4,0(Ry) 16: ADDI Rx,Rx,#8 17: ADDI Ry , Ry,#8 I8: SUB R20,R4, Rx I9 BNZ R20, Loop Latencies beyond single cycle Memory LD Memory SD Integer ADD, SUB Branches ADDD MULTD DIVD +0 +1 +10