An earlier version of the IBM mainframe, the S/390 G4, used three levels of cache.As with the z990, only the first level was on the processor chip [called the processor unit (PU)].The L2 cache was also similar to the z990. An L3 cache was on a separate chip that acted as a memory controller, and was interposed between the L2 caches and the memory cards. Table 17.4 shows the performance of a three-level cache arrangement for the IBM S/390.The purpose of this problem is to determine whether the inclusion of the third level of cache seems worthwhile. Determine the access penalty (average number of PU cycles) for a system with only an L1 cache, and normalize that value to 1.0.Then determine the normalized access penalty when both an L1 and L2 cache are used, and the access penalty when all three caches are used. Note the amount of improvement in each case and state your opinion on the value of the L3 cache.
Table 17.4 Typical Cache Hit Rate on S/390 SMP Configuration [MAK97]

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Access Penalty (PU cycles) Memory Subsystem Hit Rate (%) Li cache L2 cache L3 cache Memory Cache Size 32 KB 256 KB 2 MB 8 GB 89 14 32