Assume the system is your desktop PC and only one core on the CMP is active. Assume
Question:
a. How many DRAMs are on the DIMM if 512 Mbit DRAMs are used, and how many data I/Os must each DRAM have if only one DRAM connects to each DIMM data pin?
b. What burst length is required to support 32-byte versus 64-byte level 2 cache blocks?
c. What is the peak bandwidth ratio between the DIMMs for reads from an active page?
d. How much time is required from the presentation of the activate command until the last requested bit of data from the DRAM transitions from valid to invalid for the DDR2-533 1 GB CL = 4 DIMM?
e. What is the relative latency when using the DDR2-533 DIMM of a read requiring a bank activate versus one to an already open page, including the time required to process the miss inside the processor?
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a A 1 GB DRAM with parity or ECC effectively has 9bit by...View the full answer
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Related Book For 
Computer Architecture A Quantitative Approach
ISBN: 978-0123704900
4th edition
Authors: John L. Hennessy, David A. Patterson
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