If you ever get confused about what a register renamer has to do, go back to the assembly code you're executing, and ask yourself what has to happen for the right result to be obtained. For example, consider a three-way superscalar machine renaming these three instructions concurrently:
ADDI............. R1, R1, R1
ADDI............. R1, R1, R1
ADDI............. R1, R1, R1
If the value of R1 starts out as 5, what should its value be when this sequence has executed?

Figure 2.39 Rename table and on-the-fly register substitution logic for superscalar machines. ("src" is source, "dst" is destination.)

Figure 2.40 Sample VLIW code with two adds, two loads, and two stalls.

Transcribed Image Text:

Next avallable T reglsier Rename table This 9 appears 2, 39 table In next clock cycle 522 9 | 28 dst-F5 src1 = T6 Src2 T39 (As per Instr 1) 11 dst =12src? dst T10 src1 = T9 dst F9 SrC1 F5 12 (Similar mux--+ src2 for src 2) T14 Loop: LW R1,0(R2)LW R3,8 (R2)