An n-channel implanted transistor from the process described in Table 2.1 displays a measured output resistance of 5 MΩ at a drain current of 10 μA, biased in the active region at a V_DSof 5 V. 

Table 2.1

The drawn dimensions of the device are 100 μm by 7 μm. Find the output resistance of a second device on the same technology that has drawn dimensions of 50 μm by 12 μm and is operated at a drain current of 30 μA and a V_DS of 5 V.

Value Value n-Channel p-Channel Transistor Parameter Symbol Transistor Units 1 1016 1 105 Atoms/cm Substrate doping Gate oxide thickness NA, Np 400 400 ter Metal-silicon work function Channel mobility Minimum drawn channel length Source, drain junction depth Source, drain side diffusion Overlap capacitance per unit gate width Threshold adjust implant (box dist) -0.6 -0.1 cm?/V-s 700 3 350 Larwn X j La 3 0.6 0.6 0.3 0.3 Cd 0.35 0.35 fF/um impurity type effective depth X; 0.3 0.3 2 x 1016 Atoms/cm3 effective surface 0.9 x 1016 concentration Nominal threshold voltage Polysilicon gate doping V, Napoly 0.7 -0.7 1020 Atoms/cm 1020 concentration Poly gate sheet resistance Source, drain-bulk junction capacitances (zero bias) Source, drain-bulk junction capacitance grading R, 20 20 fF/um? Cp 0.08 0.20 0.5 0.5 coefficient Source, drain periphery capacitance (zero bias) Source, drain periphery capacitance grading coefficient C jow0 0.5 1.5 fF/um 0.5 0.5 Source, drain junction built-in potential 0.65 0.65 Q ss Atoms/cm? 10" 10!! Surface-state density dX4 Channel-length modulation 0.2 0.1 um/V dVps parameter