- The ac schematic of a common-emitter stage is shown in Fig. 7.2a. Calculate the low-frequency small-signal voltage gain Ï…o/Ï…iand use the zerovalue time-constant method to
- Repeat Problem 7.14 if a resistor of value 30 kÎ© is connected between collector and base of the transistor.Data from Prob. 7.14:The ac schematic of a common-emitter stage is shown in Fig.
- The ac schematics of a common-source stage and a common-source€“common-gate (cascode) stage are shown in Fig. 7.43 with RS= 10 kÎ© and RL= 20 kÎ©. Using the transistor
- How does the loop gain T = af of the circuit of Fig. 8.50 change as the following circuit elements change? Discuss qualitatively.(a) 50 Î© emitter resistor of the input stage(b) 500
- The ac schematic of a shunt-series feedback amplifier is shown in Fig. 8.31. Element values are RF= 1 kÎ©, RE= 100 Î©, RL1= 4 kÎ©, RS= 1/yS= 1 kÎ©, and zL=
- (a) Repeat Problem 8.17(a) with RF = 5 kΩ, RE = 200 Ω, RL1 = 10 kΩ, and ys = 0.(b) If the collector current of Q1 increases by 20 percent, what will be the approximate change in overall gain and
- Calculate the transconductance, input impedance, output impedance, and loop transmission at low frequencies of the local series-feedback stage of Fig. 8.34 with parameters RE= 200 Î©,
- Acommercial wideband monolithic feedback amplifier (the 733) is shown in Fig. 8.51. This consists of a local series-feedback stage feeding a two-stage shunt-shunt feedback amplifier. The current
- If the 723 voltage regulator is used to realize an output voltage Vo = 10 V with a 1-kΩ load, calculate the output resistance and the loop gain of the regulator. If a 500-Ω load is connected to the
- Assume the BiCMOS amplifier of Fig. 3.78 is fed from a current source. Calculate the low-frequency small-signal transresistance Ï…o/ii, the loop gain, and the input and output impedances of
- A variable-gain CMOS amplifier is shown in Fig. 8.52. Note that M4represents shunt feedback around M6. Assuming that the bias value of Viis adjusted so that VGD6= 0 V dc, calculate bias currents in
- A CMOS feedback amplifier is shown in Fig. 8.53. If the dc input voltage is zero, calculate the overall gain Ï…o/Ï…iand the output resistance. Compare your answer with a SPICE simulation. Use
- An active-cascode gain stage is shown in Fig. 8.54. Assume the amplifier A1has a voltage gain a = 1 Ã— 103and infinite input impedance. For the transistors, k€™n= 140
- Use Blackman€™s impedance formula to find the output resistance of the active-cascode current source in Fig. 8.55. Express the result in terms of gm1, gm2, ro1, ro2, and a, which is the
- Use return-ratio analysis and Blackman€™s impedance formula to find the closed-loop gain, return ratio, input resistance, and output resistance for the inverting gain amplifier in Fig.
- An ac schematic of a local shunt-shunt feedback circuit is shown in Fig. 8.57. Take RF= 100 kÎ© and RL= 15 kÎ©. For the MOS transistor, ID= 0.5 mA, W/L = 100, k€™ =
- Replace the MOS transistor in Fig. 8.57 by a npn transistor. Take RF= 2 kÎ©, RL= 2 kÎ©, Î² = 200, IC= 1 mA, rb= 0, and VA = 100 V.(a) Repeat Problem 8.28(a).(b)
- A voltage-follower feedback circuit is shown in Fig. 8.58. For the MOS transistor, ID= 0.5 mA, k€™ = 180 µA/V2, ro= ˆž, W/L = 100, |Ï•f| = 0.3 V, and Î³
- Replace the MOS transistor in Fig. 8.58 with a npn transistor. For the transistor, IC= 0.5 mA and ro= ˆž.(a) Repeat the calculations in Problem 8.30(a).(b) Repeat the calculations in
- For the noninverting amplifier shown in Fig. 8.59, R1= 1 kÎ©, and R2= 5 kÎ©. For the op amp, take Ri= 1 MÎ©, Ro= 100 Î©, and av= 1 Ã— 104.
- Calculation of return ratio begins by breaking a feedback loop at a controlled source. However, breaking a feedback loop at a controlled source is often impossible in a SPICE simulation because the
- (a) Calculate the loop gain T = af for the series-shunt feedback circuit in Fig. 8.59 using hparameter two-ports. Take R1= 200 kÎ©, and R2= 100 kÎ©. For the op amp, assume Ri=
- For the CMOS operational amplifier shown in Fig. 9.60, calculate the open-loop voltage gain, unity gain bandwidth, and slew rate. Assume the parameters of Table 2.1 with Xd= 1 µm. Assume that
- Repeat Problem 9.23, but skip the SPICE simulation. Here, M9will be used in the op amp in Fig. 6.58. Let VDD= VSS= 1.5 V and IS= 200 µA. Use L = 1 µm for all transistors, W8= W10= 150
- Repeat Problem 12.5 c when the gates of M3and M4are the CMC input, and the gate of M5 connects to a bias voltage.Data from Prob. 12.5 (c)For the op amp in Fig. 12.2, use the data from Problem
- Estimate the capture range of the PLL of Problem 10.7, assuming that it is not artificially limited by the VCO frequency range.
- A technique that allows the return ratio to be simulated using SPICE without disrupting the dc operating point is shown in Fig. 8.60 and explained in Problem 8.33.(a) Use that technique to simulate
- Assuming that the zero has been moved to infinity, determine the maximum load capacitance that can be attached directly to the output of the circuit of Fig. 9.60 and still maintain a phase margin of
- If the circuit of Fig. 9.61 is used to generate the voltage to be applied to the gate of M9in Fig. 9.60, calculate the W/L of M9required to move the right half-plane zero to infinity. Use data from
- Repeat Problem 9.21 except use the aspect ratios, supply voltages, and bias current given in Fig. 6.58 instead of the values in Fig. 9.60. Also, assume that Xd= 0.1 µm for all transistors
- (a) Calculate the full-power bandwidth of the circuit of Fig. 9.59.(b) If this circuit is connected in a non-inverting unity-gain feedback loop, sketch the output waveform Vo if Vi is a sinusoid of
- Repeat Problem 9.18 if PMOS transistors replace Q1and Q2(with no degeneration resistors). Assume that the PMOS transistors are biased to 300 µA each (IEE= 600 µA), at which bias value the
- Repeat Problem 9.16 if the circuit of Fig. 9.59 is compensated by a capacitor of 0.05 µF connected from the base of Q5to ground. Assume that the voltage gain from the base of Q5to Vois
- The input stages of an op amp are shown in the schematic of Fig. 9.59.(a) Assuming that the frequency response is dominated by a single pole, calculate the frequency where the magnitude of the
- Repeat Problem 9.14 if the circuit has negative real poles with magnitudes 100 Hz and 100 kHz and a negative real zero with magnitude 120 kHz.Data from Prob. 9.14:An op amp has two negative real
- An op amp has two negative real open-loop poles with magnitudes 100 Hz and 120 kHz and a negative real zero with magnitude 100 kHz. The low frequency open-loop voltage gain of the op amp is 100 dB.
- For the circuit of Fig. 9.41, parameter values are RF= 5 kÎ©, RE= 50 Î©, and CF= 1.5 pF. The basic amplifier of the circuit is shown in Fig. 9.42 and has two negative real poles
- Calculate and sketch the root locus for the amplifier of Problem 9.4 as f varies from 0 to 1. Estimate the value of f causing instability and check using the Nyquist criterion.Data from Prob. 9.4:An
- An amplifier has gain a0 = 200 and its transfer function has three negative real poles with magnitudes 1 MHz, 3 MHz, and 4 MHz. Calculate and sketch the root locus when feedback is applied as f
- Repeat Problem 9.6 for the amplifier of Problem 9.4.Data from Prob. 9.6:The amplifier of Problem 9.5 is to be compensated by reducing the magnitude of the most dominant pole.(a) Calculate the
- The slew rate of the circuit of Fig. 9.59 is to be increased by using 10 kÎ© resistors in the emitters Q1and Q2. If the same unity-gain frequency is to be achieved, calculate the new value
- Repeat Problem 9.25 except, for the op amp, use the aspect ratios, supply voltages, and bias current given in Fig. 6.58 instead of the values in Fig. 9.60. Also, for the bias circuit, use the aspect
- The CMOS circuit of Fig. 9.56 is to be used as a high-slew-rate op amp. A load capacitance of CL= 10 pF is connected from Voto ground. Supply voltages are ± 5 V and I1= 20 µA. Devices
- Using the basic topology of Fig. 8.53, design a CMOS feedback amplifier with Ri= ˆž, Ro< 30 Î©, Av= Ï…o/Ï…i= 10, and small-signal bandwidth
- Determine the compensation capacitor for the two-stage op amp in the example in Section 9.4.3 that gives a 60° phase margin.
- The Miller-compensated two-stage op amp in Fig. 9.25 can be modeled as shown in Fig. 9.26. In the model, let gm1= 0.5 mA/V, R1= 200 kÎ©, gm6= 2 mA/V, R2= 100 kÎ©, C1= 0.1 pF,
- Repeat Problem 9.31(a) for the common-gate compensation scheme in Fig. 9.22 a.Data from Prob. 9.31 (a):The Miller-compensated two-stage op amp in Fig. 9.25 can be modeled as shown in Fig. 9.26. In
- The simple model for the common-gate M11in Fig. 9.22 b has zero input impedance. Show that if the common-gate stage M11is modeled with nonzero input impedance, the compensation scheme in Fig. 9.22 a
- Plot a locus of the poles of (9.27) as C varies from 0 to ∞. Use R1 = 200 kΩ, gm = 2 mA/V, R2 = 100 kΩ, C1 = 0.1 pF, and C2 = 8 pF.
- For the three-stage op amp with nested Miller compensation in Fig. 9.30c, determine the values of the compensation capacitors that give a 45—¦ phase margin when the op amp is in a
- For the three-stage op amp with nested Miller compensation in Fig. 9.30c, determine the values of the compensation capacitors that give a 60—¦ phase margin when the op amp is in a
- The single-stage op amp in Fig. 9.54 has a 45° phase margin when the op amp is in a unity-gain negative feedback loop (f=1) with an output load capacitance CL=2 pF. What value of CLwill give a
- The single-stage op amp in Fig. 9.54 has a nondominant pole p2with |p2|=200 Mrad/s. The op amp is in a unity-gain negative feedback loop (f = 1).(a) If gm1 = 0.3 mA/V, what value of CL givesa
- The feedback circuit in Fig. 9.55 is a switched-capacitor circuit during one clock phase.Assume the op amp is the telescopic-cascode op amp in Fig. 9.54. Take CL= 1.5 pF, CI = 4 pF, CS = 0.4 pF, and
- Calculate the return ratio for the feedback circuit in Fig. 9.62. Assume that the amplifier voltage gain is constant with av> 0. Show that this feedback circuit is always stable if each impedance
- Calculate the return ratio for the integrator in Fig. 9.63. Show that this feedback circuit is stable for all values of R and C if av(s) has two left half-plane poles and av(s = 0) > 0.Figure
- Calculate the return ratio for the inverting amplifier in Fig. 9.64. Here, the controlled source and C in form a simple op-amp model. Assume av(s) = 1000/[(1 + s/100) (1 + s/106)].(a) Assume the
- Repeat Problem 9.43 for the circuit in Fig. 9.64 with Cin= 4 pF. Inject the test sources on the left-hand side of the feedback resistor. Use av(s) from Problem 9.42. Compare the simulation results
- Consider a two-stage CMOS op amp modeled by the equivalent circuit in Fig. 9.18, where is = gmvidand vidis the differential op-amp input. Let gm= 19.7mA/V, R1 = R2= 6.67 kÎ©, and
- Sketch the dc transfer curve Iout versus V2 for the Gilbert multiplier of Fig. 10.4 for V1 equal to 0.1VT , 0.5VT , and VT .
- For the emitter-coupled pair of Fig. 10.1, determine the magnitude of the dc differential input voltage required to cause the slope of the transfer curve to be different by 1 percent from the slope
- Assume that a sinusoidal voltage signal is applied to the emitter-coupled pair of Fig. 10.1. Determine the maximum allowable magnitude of the sinusoid such that the magnitude of the third harmonic in
- Determine the worst-case input offset voltage of the voltage-current converter shown in Fig. 10.23. Assume that the op amps are ideal, that the resistors mismatch by ±0.3 percent and that
- Determine the dc transfer characteristic of the circuit of Fig. 10.24. Assume that Z = 0.1XY for the multiplier.Fig. 10.24 ret Analog z multiplier x W- Vin Vout
- A phase-locked loop has a center frequency of 105 rad/s, a KO of 103 rad/V-s, and a KD of 1 V/rad. There is no other gain in the loop. Determine the loop bandwidth in the first-order loop
- For the same PLL of Problem 10.6, design a loop filter with a zero that gives a crossover frequency for the loop gain of 100 rad/s. The loop phase shift at the loop crossover frequency should be
- An FM demodulator using a PLL has a center frequency of 2 kHz and is implemented as a first-order loop. The input signal alternates between 1.95 kHz and2.05 kHz at a rate of 200 Hz with instantaneous
- Design a voltage-controlled oscillator based on the circuit of Fig. 10.21a. The center frequency is to be 10 kHz, C = 0.01µF, and VCC = 5 V. For the transistors Î² = 100 and IS=
- Using the methods of Section 10.4, design a circuit with a transfer characteristicIo = KI3/2iforIi ≥0. The input bias voltage must be≥VBE, and the output bias voltage is equal to 2VBE. The
- Show that the CMOS circuit of Fig. 10.25 realizes a square-law transfer characteristic from Vito Io assuming that the MOSFETs have square-law characteristics. Specify the range of Viover which
- Calculate the noise-voltage spectral density in V2/Hz at vofor the circuit in Fig. 11.48, and thus calculate the total noise in a 100-kHz bandwidth. Neglect capacitive effects, flicker noise, and
- If the diode in Fig. 11.48 shows flicker noise, calculate and plot the output noise voltage spectral density at voin V2/Hz on log scales from f = 1 Hz to f =10 MHz. Flicker noise data: in (11.7) use
- Repeat Problem 11.2 if a 1000-pF capacitor is connected across the diode. Compare your result with a SPICE simulation.Repeat problem 11.2If the diode in Fig. 11.48 shows flicker noise, calculate and
- The ac schematic of an amplifier is shown in Fig. 11.49. The circuit is fed from a current source iSand data are as follows:RS =1 k „¦ RL= 10 k „¦ IC = 1 mAÎ²
- Calculate the total input- and output-referred noise voltages at 10 Hz, 100 kHz, and 1 GHz for the common-source amplifier shown in Fig. 7.2b. Assume that W = 100 µm, L = 1 µm, ID= 100
- Calculate equivalent input noise voltage and current generators for the circuit of Fig. 11.49 (omitting RS). Using these results, calculate the total equivalent input noise current in a 2-MHz
- Four methods of achieving an input impedance greater than 100 kÎ© are shown in the ac schematics of Fig. 11.50.(a) Neglecting flicker noise and capacitive effects, derive expressions for
- Neglecting capacitive effects, calculate equivalent input noise voltage and current generators for circuit (iv) of Fig. 11.50, assuming that the spectral density of the flicker noise in the MOS
- The ac schematic of a low-input-impedance common-base amplifier is shown in Fig. 11.52.(a) Calculate the equivalent noise voltage and current generators of this circuit at the emitter of Q1 using IC1
- A super-Î² input stage is shown in Fig. 11.53a.(a) Neglecting flicker noise and capacitive effects, calculate the equivalent input noise voltage and current generators Ï…2 and i2
- Repeat Problem 11.11 if the bipolar transistors are replaced by MOS transistors with IG= 0.1 fA and gm= 0.5 mA/V. Assume Cgs= 0.Data from Prob. 11.11:A super-Î² input stage is shown in
- If a 100-pF capacitor is connected across the diode in Fig. 11.48, calculate the noise bandwidth of the circuit and thus calculate the total output noise at Ï…o. Neglect flicker noise and
- A differential input stage is shown in Fig. 11.54.(a) Neglecting flicker noise, calculate expressions for the equivalent input noise voltage and current generators at the base of Q1. Use SPICE to
- Calculate the source resistance giving minimum noise figure and the corresponding noise figure in decibels for a bipolar transistor with parameters(a) IC = 2 mA
- Repeat Problem 11.15 if the transistor has a flicker noise corner frequency of 1 kHz. Calculate spot noise figure at 500 Hz.Data from Prob. 11.15:Calculate the source resistance giving minimum noise
- Repeat Problem 11.15 if the transistor has a 1-kΩ emitter resistor.Data from Prob. 11.15:Calculate the source resistance giving minimum noise figure and the corresponding noise figure in decibels
- (a) Neglecting flicker noise and capacitive effects, calculate the noise figure in decibels of the circuit of Fig. 11.54 with RS = 50 Ω.(b) If RS were made equal to (i) 100 Ω or (ii) 200 kΩ, would
- (a) A shunt-feedback amplifier is shown in Fig. 11.55. Using equivalent input noise generators for the device, calculate the spot noise figure of this circuit in decibels for RS= 10 kÎ©
- (a) Neglecting capacitive effects, calculate the noise figure in decibels of the circuit of Fig. 11.52 with RS= 5 kÎ©. Use data as in Problem 11.10.(b) If the flicker noise corner
- Neglecting flicker noise, calculate the total equivalent input noise voltage for the MC1553 shown in Figure 8.21a. Use Î² = 100, rb= 100 Î© and assume a sharp cutoff in the
- Calculate the total equivalent input noise current for the shunt-shunt feedback circuit of Fig. 8.48 in a bandwidth from 0.01 Hz to 100 kHz. Use the MOS transistor data in Problem 11.5. Ignore
- Repeat Problem 11.22 if the MOS transistors in Fig. 8.48 are replaced by bipolar transistors. Assume that Î² = 200, rb= 300, IC= 1 mA and the flicker noise corner frequency is fa= 5 kHz.
- The BiCMOS amplifier of Fig. 3.78 is to be used as a low-noise transimpedance amplifier. The input is fed from a current source with a shunt source capacitance of CS= 1 pF. Assuming that CSand Cgs1=
- A MOS current source of the type shown in Fig. 4.4 is to be designed to achieve minimum output current noise. The two transistors must be identical and the total gate area of the two transistors
- Calculate the equivalent input noise volt-age at 100 Hz, 1 kHz, and 10 kHz for the CMOS op amp shown in Fig. 6.58. Use the MOS parameters in Table 2.4, and assume that Xd= 0.1 µm at the
- Use SPICE to verify the noise analysis of the NE5234 op amp given in Section 11.8. Then add flicker noise generators assuming a = 1 in (11.13) and the transistor flicker noise corner frequency is 1
- (a) At what frequency are the noise spectral densities, i̅2g /∆f, for the gate-current noise in (11.15) and (11.16) equal? Assume that W = 50 µm, L = 0.5 µm, IG = 0.05 fA, ID = 100
- What are the swing limits for each output of the differential amplifier in Fig. 12.2? Use |Vov| = 0.2 V for all transistors and Vtn= ˆ’Vtp= 0.6 V. Assume VDD= VSS= 2.5 V, Vic= 0 and
- Repeat 12.1 for the two-stage op amp in Fig. 12.23. Assume that switched-capacitor CMFB is used, which does not limit the output swing. Use the data in Problem 12.1.Data from Prob. 12.1:What are the
- A balanced fully differential circuit displays only odd-order nonlinearity. Use SPICE to verify this fact for the op amp in the example in Section 12.6.1.(a) Either use SPICE to find the distortion

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