The single stage op amp in Fig 9 54 has a 45 deg phase margin when the op amp is in a unity gain negative feedback loop (f 1) with an output load capacitance C L 2 pF What value of C L will give a 60 deg phase margin (Assume that the capacitance at the op amp output is dominated by C L and the op amp gain a Iuml (s) can be modeled as having two poles ) Figure 9 middot 54 VDD M4 V81 MAA Ve d2A Vr2 2 M1A in M2 , in O ITAIL Vss

Question: The single-stage op amp in Fig. 9.54 has a 45° phase margin when the op amp is in a unity-gain negative feedback loop (f=1) with

The single-stage op amp in Fig. 9.54 has a 45° phase margin when the op amp is in a unity-gain negative feedback loop (f=1) with an output load capacitance C_L=2 pF. What value of C_Lwill give a 60° phase margin? (Assume that the capacitance at the op-amp output is dominated by C_Land the op-amp gain a_Ï…(s) can be modeled as having two poles.)

Figure 9·54:

VDD M4 Мз V81 MAA Мзл Ve d2A Vr2 М2л M1A in- M2 м, in+ O ITAIL -Vss

VDD M4 V81 MAA Ve d2A Vr2 2 M1A in- M2 , in+ O ITAIL -Vss

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