Consider Problem 9.54 except that the cache uses a write-back mode. On average 25% of cache lines are dirty (have been modified).

Data in Problem 9.54,

A computer has a cache with a hit ratio of 95% and a line size of four 32-bit words. The average processor cache access rate is 100 million/s. Twenty percent of CPU operations are loads/stores with 30% writes and 70% reads). The cache employs a write through mechanism and a line is replaced on a write miss. What is the bandwidth of the 32-bit CPU-memory bus used under these conditions?