Demonstrate how a compiler might translate the following fragment of code into a form that can run on a VLIW processor that specifies three operations per instruction word (i.e., three instructions per bundle in ltanium terminology). You may perform instruction reordering. Assume that the latency for a load is three cycles and the latency for a multiply is two cycles (i.e., the load takes three cycles in total). Use a NOP whenever an instruction slot cannot be filled. 

Repeat the same exercise, but assume that the VLIW processor can perform only one memory access operation per cycle. Assume that the memory unit is fully pipelined; that is, it has a latency of three cycles but the next memory operation can begin in the following cycle.

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MOV 17,#4 LDR r1, [12] LDR r3, [14] LDR r5, [16] ADD rl, rl, r3 ADD rl, rl, r5 DIV rl, rl, r7 ADD r2, #8, r2 ADD r4, #8, 14 ADD r6 , #8 , r6