For each part of this exercise, the initial cache and memory state are assumed to initially have the contents shown in Figure 5.37. Each part of this exercise specifies a sequence of one or more CPU operations of the form

Line number 0 1 2 3 Core 0 Coherency state I S M 1 Address Data AC00 0010 AC08 0008 AC10 0030 AC18 0010 Cache line 0 1 2 3 Core 1 Coherency state 1 M 1 S Address AC00 0010 AC08 0008 AC10 0010 AC18 0018 AC20 0020 AC28 0028 AC30 0030 Data Memory Figure 5.37 Multicore (point-to-point) multiprocessor. Address AC00 AC28 AC10 AC18 Data 0010 0068 0010 0018 Cache line 0 1 2 3 Core3 Coherency stato S S 1 1 Address Data AC20 20 AC08 0008 AC10 0010 AC18 0010