Whereas larger caches have lower miss rates, they also tend to have longer hit times.
Assume a direct-mapped 8 KB cache has 0.22 ns hit time and miss rate m1; also assume a 4-way associative 64 KB cache has 0.52 ns hit time and a miss rate m2.

a. If the miss penalty is 100 ns, when would it be advantageous to use the smaller cache to reduce the overall memory access time?

b. Repeat part (a) for miss penalties of 10 and 1000 cycles. Conclude when it might be advantageous to use a smaller cache.