Exercise 1.5 Consider two different implementations, P1 and P2, of the same instruction set.

There are fi ve classes of instructions (A, B, C, D, and E) in the instruction set. The clock rate and CPI of each class is given below.

Clock rate CPI Class A CPI Class B CPI Class C CPI Class D CPI Class E

a. P1 1.0 GHz 1 2 3 4 3 P2 1.5 GHz 2 2 2 4 4

b. P1 1.0 GHz 1 1 2 3 2 P2 1.5 GHz 1 2 3 4 3 1.5.1 [5] <1.4> Assume that peak performance is defi ned as the fastest rate that a computer can execute any instruction sequence. What are the peak performances of P1 and P2 expressed in instructions per second?
1.5.2 [5] <1.4> If the number of instructions executed in a certain program is divided equally among the classes of instructions except for class A, which occurs twice as often as each of the others. Which computer is faster? How much faster is it?
1.5.3 [5] <1.4> If the number of instructions executed in a certain program is divided equally among the classes of instructions except for class E, which occurs twice as often as each of the others? Which computer is faster? How much faster is it?
The table below shows instruction-type breakdown for different programs. Using this data, you will be exploring the performance tradeoffs with different changes made to a MIPS processor.
# Instructions Compute Load Store Branch Total

a. Program 1 1000 400 100 50 1550

b. Program 4 1500 300 100 100 1750 1.5.4 [5] <1.4> Assuming that computes take 1 cycle, loads and store instructions take 10 cycles, and branches take 3 cycles, fi nd the execution time of each program on a 3 GHz MIPS processor.
1.5.5 [5] <1.4> Assuming that computes take 1 cycle, loads and store instructions take 2 cycles, and branches take 3 cycles, fi nd the execution time of each program on a 3 GHz MIPS processor.
1.5.6 [5] <1.4> Assuming that computes take 1 cycle, loads and store instructions take 2 cycles, and branches take 3 cycles, what is the speed-up of a program if the number of compute instruction can be reduced by one-half?