Computer Organization And Design The Hardware Software Interface 4th Edition David A. Patterson, John L. Hennessy - Solutions

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1. What is accounting
Exercise 7.23 Assume a quad-core computer system can process database transactions at a steady state rate of requests per second. Also assume that each transaction takes, on average, a fi xed amount of time to process. The following table shows pairs of transaction latency and processing
Exercise 7.22 In future systems, we expect to see heterogeneous computing platforms constructed out of heterogeneous CPUs. We have begun to see some appear in the embedded processing market in systems that contain both fl oating-point DSPs and microcontroller CPUs in a multichip module
Exercise 7.21 When performing computations on sparse matrices, latency in the memory hierarchy becomes much more of a factor. Sparse matrices lack the spatial locality in the data stream typically found in matrix operations. As a result, new matrix representations have been proposed.One of the
Exercise 7.20 Benchmarking is a fi eld of study that involves identifying representative workloads to run on specifi c computing plat forms in order to be able to objectively compare performance of one system to another. In this exercise we will com pare two classes of benchmarks: the Whetstone CPU
Exercise 7.19 Refer to Figure 7.9b that shows an n-cube interconnect topology of order 3 that interconnects eight nodes. One attractive feature of an n-cube interconnection network topology is its ability to sustain broken links and still provide connectivity.7.19.1 [10] Develop an equation that
Exercise 7.18 AMD has recently announced that they will be integrating a graphics processing unit with their x86 cores in a single package, though with different clocks for each of the cores. This is an example of a heterogeneous multiprocessor system which we expect to see produced commericially
Exercise 7.17 Download the CUDA Toolkit and SDK from www.nvidia.com/object/cuda_get.html.Make sure to use the “emurelease” (Emulation Mode) version of the code (you will not need actual NVIDIA hardware for this assignment). Build the example programs provided in the SDK, and confi rm that they
Exercise 7.16 Assume we want to execute the DAXP loop show on page 651 in MIPS assembly on the NVIDIA 8800 GTX GPU described in this chapter. In this problem, we will assume that all math operations are performed on single pre cision fl oatingpoint numbers (we will rename the loop SAXP). Assume
Exercise 7.15 A systolic array is an example of an MISD machine. A systolic array is a pipeline network or “wavefront” of data processing elements. Each of these elements does not need a program counter since execution is triggered by the arrival of data.Clocked systolic arrays compute in
Exercise 7.14 We would like to execute the loop below as effi ciently as possible. We have two different machines, an MIMD machine and an SIMD machine.for (i=0; i < 2000; i++)for (j=0; j
Exercise 7.13 Virtualization software is being aggressively deployed to reduce the costs of managing today’s high performance serv ers. Companies like VMWare, Microsoft, and IBM have all developed a range of virtualization products. The general concept, described in Chapter 5, is that a
Exercise 7.12 Consider the following three CPU organizations:CPU SS: A 2-core superscalar microprocessor that provides out-of-order issue capabilities on two functional units (FUs). Only a single thread can run on each core at a time.CPU MT: A fi ne-grained multithreaded processor that allows
Exercise 7.11 The dining philosopher’s problem is a classic problem of synchronization and concurrency. The general problem is stated as philosophers sitting at a round table doing one of two things: eating or thinking. When they are eating, they are not thinking, and when they are thinking, they
Exercise 7.10 On a CC-NUMA system, the cost of accessing nonlocal memory can limit our ability to utilize multiprocessing ef fectively. The following table shows the costs associated with access data in local memory versus nonlocal memory and the locality of our application expresses as the
Exercise 7.9 Considering the CC-NUMA system described in Exercise 7.8, assume that the system has four nodes, each with a single-core CPU (each CPU has its own L1 data cache and L2 data cache). The L1 data cache is store-through, though the L2 data cache is write-back. Assume that system has a
Exercise 7.8 In a cache-coherent, nonuniform-memory access (CC-NUMA) shared memory system, CPUs and physical memory are divided across compute nodes. Each CPU has local caches. To maintain the coherency of memory, we can add status bits into each cache block, or we can in troduce dedicated memory
Exercise 7.7 Consider the following portions of two different programs running at the same time on four processors in a symmetric multicore processor (SMP). Assume that before this code is run, both x and y are 0.Core 1: x = 2;Core 2: y = 2;Core 3: w = x + y + 1;Core 4: z = x + y;7.7.1 [10] What
Exercise 7.6 Matrix multiplication plays an important role in a number of applications. Two matrices can only be multiplied if the number of columns of the fi rst matrix is equal to the number of rows in the second.Let’s assume we have an m × n matrix A and we want to multiply it by an n × p
Exercise 7.5 You are trying to bake three blueberry pound cakes. Cake ingredients are as follows:1 cup butter, softened 1 cup sugar 4 large eggs 1 teaspoon vanilla extract 1/2 teaspoon salt 1/4 teaspoon nutmeg 1 1/2 cups fl our 1 cup blueberries The recipe for a single cake is as follows:Preheat
Exercise 7.4 Consider the following recursive mergesort algorithm (another classic divide and conquer algorithm). Mergesort was fi rst described by John von Neumann in 1945.The basic idea is to divide an unsorted list x of m elements into two sublists of about half the size of the original list.
Exercise 7.3 Consider the following piece of C code:for (j=2;j
Exercise 7.2 Many computer applications involve searching through a set of data and sorting the data. A number of effi cient search ing and sorting algorithms have been devised in order to reduce the runtime of these tedious tasks. In this problem we will consider how best to parallelize these
Exercise 7.1 First, write down a list of your daily activities that you typically do on a weekday.For instance, you might get out of bed, take a shower, get dressed, eat breakfast, dry your hair, brush your teeth, etc. Make sure to break down your list so you have a minimum of 10 activities.7.1.1
Exercise 6.20 Day-to-day evaluation and maintenance of operational computer systems involves many of the concepts discussed in Chapter 6. Explore the intricacies of evaluating systems by exploring the following questions.6.20.1 [20] Confi gure the Sun Fire x4150 to provide 10 terabytes of storage
Exercise 6.19 For disks in the table in Exercise 6.18, assume that your vendor offers a RAID 0 confi guration that will increase storage system throughput by 70% and a RAID 1 confi guration that will drop AFR of disk pairs by 2. Assume that the cost of each solution is 1.6 times the original
Exercise 6.18 Measurements and statistics provided by storage vendors must be carefully interpreted to gain meaningful predictions about their system behavior. The following table provides data for various disk drives.# of Drives Hours/Drive Hours/Failurea. 1000 8,760 1,000,000b. 1000 10,512
Exercise 6.17 Determining the performance of a single server with relatively complete data is an easy task. However, when comparing servers from different vendors providing different data, choosing among alternatives can be diffi cult. Explore the process of fi nding and evaluating servers by
Exercise 6.16 The emergence of Web servers for ecommerce, online storage, and communication has made disk servers critical applications. Availability and speed are well-known metrics for disk servers, but power consumption is becoming increasingly important.Answer the questions about confi guration
Exercise 6.15 RAID 3, RAID 4, and RAID 5 all use parity system to protect blocks of data. Specifi cally, a parity block is associated with a collection of data blocks. Each row in the following table shows the values of the data and parity blocks, as described in Figure 6.13.New D0 D0 D1 D2 D3 Pa.
Exercise 6.14 RAID is among the most popular approaches to parallelism and redundancy in storage systems. The name Redundant Arrays of Inexpensive Disks implies several things about RAID arrays that we will explore in the context of the following activities.a. Online Database Servicesb. Sound
Exercise 6.13 Benchmarks play an important role in evaluating and selecting peripheral devices.For benchmarks to be useful, they must exhibit properties similar to those experienced by a device under normal use. Explore benchmarks and device selection by answering questions about the following
Exercise 6.12 Metrics for I/O performance may vary dramatically from application to application.Where the number of transactions processed dominates performance in some situations, data throughput dominates in others. Explore I/O performance evaluation by answering the questions for the following
Exercise 6.11 Direct Memory Access (DMA) allows devices to access memory directly rather than working through the CPU. This can dramatically speed-up the performance of peripherals, but adds complexity to memory system implementations. Explore DMA implications by answering the questions about the
Exercise 6.10 Section 6.6 defi nes an eight-step process for handling interrupts. The Cause and Status registers together provide information on the cause of the interrupt and the status of the interrupt handling system. Explore interrupt handling by answering the questions about the following
Exercise 6.9 Communicating with I/O devices is achieved using combinations of polling, interrupt handling, memory mapping, and special I/O commands. Answer the questions about communicating with I/O subsystems for the following applications using combinations of these techniques.a. Video Game
Exercise 6.8 Among the most common bus types used in practice today are FireWire (IEEE 1394), USB, PCI, and SATA. Although all four are asynchronous, they are implemented in different ways giving them different characteristics. Explore different bus structures by answering questions about the buses
Exercise 6.7 I/O can be performed either synchronously or asynchronously. Explore the differences by answering performance questions about the following peripherals.a. Mouseb. Memory Controller 6.7.1 [5] What would be the most appropriate bus type (synchronous or asynchronous) for handling
Exercise 6.6 Explore the nature of Flash memory by answering the questions related to performance for Flash memories with the following characteristics.Data Transfer Rate Controller Transfer Ratea. 34 MB/s 480 MB/sb. 30 MB/s 500 MB/s 6.6.1 [10] Calculate the average time to read or write a
Exercise 6.5 Flash memory is one of the fi rst true competitors for traditional disk drives. Explore the implications of Flash memory by answering questions about the following applications.a. Online NASA Satellite Databaseb. Video Gaming System 6.5.1 [5] As we move toward solid state drives
Exercise 6.4 Ultimately, storage system design requires consideration of usage scenarios as well as disk parameters. Different situations require different metrics. Let’s try to systematically evaluate disk systems. Explore differences in how storage systems should be evaluated by answering the
Exercise 6.3 Average and minimum times for reading and writing to storage devices are common measurements used to compare devices. Using techniques from Chapter 6, calculate values related to read and write time for disks with the following characteristics.Average Seek Time RPM Disk Transfer Rate
Exercise 6.2 Mean Time Between Failures (MTBF), Mean Time To Replacement (MTTR), and Mean Time To Failure (MTTF) are useful metrics for evaluating the reliability and availability of a storage resource. Explore these concepts by answering the questions about devices with the following metrics.MTTF
Exercise 6.1 Figure 6.2 describes numerous I/O devices in terms of their behavior, partner, and data rate. However, these classifi cations often do not provide a complete picture of data fl ow within a system. Explore device classifi cations for the following devices.a. Video Gameb. Handheld GPS
Exercise 5.18 In this exercise we show the defi nition of a web server log and examine code optimizations to improve log processing speed. The data structure for the log is defi ned as follows:struct entry {int srcIP; // remote IP address char URL[128]; // request URL (e.g., “GET
Exercise 5.17 Both Barcelona and Nehalem are chip multiprocessors (CMPs), having multiple cores and their caches on a single chip. CMP on-chip L2 cache design has interesting tradeoffs. The following table shows the miss rates and hit laten cies for two benchmarks with private versus shared L2
Exercise 5.14 One of the biggest impediments to widespread use of virtual machines is the performance overhead incurred by run ning a virtual machine. The table below lists various performance parameters and application behavior.Base CPI Priviliged O/S accesses per 10,000 instructions Performance
Exercise 5.13 To support multiple virtual machines, two levels of memory virtualization are needed. Each virtual machine still con trols the mapping of virtual address (VA) to physical address (PA), while the hypervisor maps the physical address (PA) of each virtual machine to the actual machine
Exercise 5.12 In this exercise, we will examine how replacement policies impact miss rate.Assume a two-way set-associative cache with four blocks. You may fi nd it helpful to draw a table like those found on page 483 to solve the problems in this exercise, as demonstrated below on the address
Exercise 5.11 In this exercise, we will examine space/time optimizations for page tables. The following table shows parameters of a virtual memory system.Virtual address (bits) Physical DRAM installed Page size PTE size (byte)a. 32 4 GB 8 KB 4b. 64 16 GB 4 KB 8 5.11.1 [10] For a single-level page
Exercise 5.10 As described in Section 5.4, virtual memory uses a page table to track the mapping of virtual addresses to physical addresses. This exercise shows how this table must be updated as addresses are accessed. The following table is a stream of virtual addresses as seen on a system. Assume
Exercise 5.9 For a high-performance system such as a B-tree index for database, the page size is determined mainly by the data size and disk performance. Assume that on average a B-tree index page is 70% full with fi x-sized entries. The utility of a page is its B-tree depth, calculated as log2
Exercise 5.8 This exercise examines the impact of different cache designs, specifi cally comparing associative caches to the direct-mapped caches from Section 5.2. For these exercises, refer to the table of address streams shown in Exercise 5.3.5.8.1 [10] Using the references from Exercise 5.3,
Exercise 5.7 In this exercise, we will look at the different ways capacity affects overall performance.In general, cache access time is proportional to capacity. Assume that main memory accesses take 70 ns and that memory accesses are 36% of all instructions.The following table shows data for L1
Exercise 5.6 Media applications that play audio or video fi les are part of a class of workloads called “streaming” workloads; i.e., they bring in large amounts of data but do not reuse much of it. Consider a video streaming workload that accesses a 512 KB working set sequentially with the
Exercise 5.5 Recall that we have two write policies and write allocation policies, their combinations can be implemented at either in L1 or L2 cache.L1 L2a. Write-back, write allocate Write-through, non write allocateb. Write-back, write allocate Write-through, write allocate 5.5.1 [5] Buffers are
Exercise 5.4 For a direct-mapped cache design with 32-bit address, the following bits of the address are used to access the cache.Tag Index Offseta. 31–10 9–4 3–0b. 31–12 11–15 4–0 5.4.1 [5] What is the cache line size (in words)?5.4.2 [5] How many entries does the cache have?5.4.3
Exercise 5.3 Caches are important to providing a high performance memory hierarchy to processors. Below is a list of 32-bit mem ory address references, given as word addresses.a. 1, 134, 212, 1, 135, 213, 162, 161, 2, 44, 41, 221b. 6, 214, 175, 214, 6, 84, 65, 174, 64, 105, 85, 215 5.3.1 [10] For
Exercise 5.2 In this exercise we look at memory locality properties of matrix computation. The following code is written in C, where elements within the same row are stored contiguously.a. for (I=0; I
Exercise 5.1 In this exercise we consider memory hierarchies for various application, listed in the following table.a. Web browsingb. Online banking 5.1.1 [10] Assuming both client and server are involved in the process, fi rst name the client and server systems. Where can caches be placed to
Exercise 4.39 Problems in this exercise assume that, during an execution of the program, processor cycles are spent in the following way. A cycle is “spent” on an instruction if the processor completes that type of instruction in that cycle; a cycle is “spent”on a stall if the processor
Exercise 4.38 This exercise explores energy effi ciency and its relationship with performance.Problems in this exercise assume the following energy consumption for activity in Instruction Memory, Registers, and Data Memory. You can assume that the other components of the datapath spend a negligible
Exercise 4.37 This exercise explores some of the tradeoffs involved in pipelining, such as clock cycle time and utilization of hardware resources. The fi rst three problems in this exercise refer to the following MIPS code. The code is written with an assumption that the processor does not use
Exercise 4.36 This exercise is intended to help you better understand the last pitfall from Section 4.13—failure to consider pipelining in instruction set design. The fi rst four problems in this exercise refer to the following new MIPS instruction:Instruction Interpretationa. lwinc Rt,Offset(Rs)
Exercise 4.35 This exercise is intended to help you better understand the relationship between ISA design and pipelining. Problems in this exercise assume that we have a multiple-issue pipelined processor with the following number of pipeline stages, instructions issued per cycle, stage in which
Exercise 4.34 This exercise is designed to help you understand the discussion of the “Pipelining is easy” fallacy from Section 4.13. The fi rst four problems in this exercise refer to the following MIPS instruction:Instruction Interpretationa. add Rd,Rs,Rt Reg[Rd]=Reg[Rs]+Reg[Rt]b. lw
Exercise 4.33 This exercise explores how branch prediction affects performance of a deeply pipelined multiple-issue processor. Problems in this exercise refer to a processor with the following number of pipeline stages and instructions issued per cycle:Pipeline depth Issue widtha. 10 4b. 25 2
Exercise 4.32 Problems in this exercise assume that branches represent the following fraction of all executed instructions, and the following branch predictor accuracy. Assume that the processor is never stalled by data and resource dependences, i.e., the processor always fetches and executes the
Exercise 4.31 Problems in this exercise refer to the following loop, which is given as x86 code and also as a MIPS translation of that code. You can assume that this loop executes many iterations before it exits. When determining performance, this means that you only need to determine what the
Exercise 4.30 In this exercise, we make several assumptions. First, we assume that an N-issue superscalar processor can execute any N instructions in the same cycle, regardless of their types. Second, we assume that every instruction is independently chosen, without regard for the instruction that
Exercise 4.29 In this exercise, we consider the execution of a loop in a statically scheduled superscalar processor. To simplify the exercise, assume that any combination of instruction types can execute in the same cycle, e.g., in a 3-issue superscalar, the three instructions can be three ALU
Exercise 4.28 In this exercise we compare the performance of 1-issue and 2-issue processors, taking into account program transformations that can be made to optimize for 2-issue execution. Problems in this exercise refer to the following loop (written in C):C codea. for(i=0;!=j;i++)b[i]=a[i];b.
Exercise 4.27 This exercise examines how exception handling interacts with branch and load/store instructions. Problems in this exercise refer to the following branch instruction and the corresponding delay slot instruction:Branch and delay slota. beq $1,$0,Label sw $6,50($1)b. beq $5,$0,Label nor
Exercise 4.26 This exercise explores how exception handling affects control unit design and processor clock cycle time. The fi rst three problems in this exercise refer to the following MIPS instruction that triggers an exception:Instruction Exceptiona. add $0,$1,$2 Arithmetic overfl owb. lw
Exercise 4.24 This exercise examines the accuracy of various branch predictors for the following repeating pattern (e.g., in a loop) of branch outcomes:Branch outcomesa. T, T, NT, Tb. T, T, T, NT, NT 4.24.1 [5] What is the accuracy of always-taken and always-not-taken predictors for this sequence
Exercise 4.23 The importance of having a good branch predictor depends on how often conditional branches are executed. Together with branch predictor accuracy, this will determine how much time is spent stalling due to mispredicted branches. In this exercise, assume that the breakdown of dynamic
Exercise 4.22 This exercise is intended to help you understand the relationship between delay slots, control hazards, and branch execution in a pipelined processor. In this exercise, we assume that the following MIPS code is executed on a pipelined processor with a fi ve-stage pipeline, full
Exercise 4.20 Problems in this exercise refer to the following instruction sequences:Instruction sequencea. lw $1,40($2)add $2,$3,$3 add $1,$1,$2 sw $1,20($2)b. add $1,$2,$3 sw $2,0($1)lw $1,4($2)add $2,$2,$1 4.20.1 [5] Find all data dependences in this instruction sequence.4.20.2 [10] Find all
Exercise 4.19 This exercise is intended to help you understand the cost/complexity/performance tradeoffs of forwarding in a pipelined processor. Problems in this exercise refer to pipelined datapaths from Figure 4.45. These problems assume that, of all instructions executed in a processor, the
Exercise 4.18 The fi rst three problems in this exercise refer to the execution of the following instruction in the pipelined datapath from Figure 4.51, and assume the following clock cycle time, ALU latency, and Mux latency:Instruction Clock cycle time ALU Latency Mux Latencya. add $1,$2,$3 100ps
Exercise 4.17 Problems in this exercise assume that instructions executed by a pipelined processor are broken down as follows:add beq lw swa. 50% 25% 15% 10%b. 30% 15% 35% 20%4.17.1 [5] Assuming there are no stalls and that 60% of all conditional branches are taken, in what percentage of clock
Exercise 4.16 The fi rst three problems in this exercise refer to the following MIPS instruction:Instructiona. lw $1,40($6)b. add $5,$5,$5 4.16.1 [5] As this instruction executes, what is kept in each register located between two pipeline stages?4.16.2 [5] Which registers need to be read, and
Exercise 4.15 In this exercise, we examine how the ISA affects pipeline design. Problems in this exercise refer to the following new instruction:a. bezi (Rs),Label if Mem[Rs] = 0 then PC=PC+Offsb. swi Rd,Rs(Rt) Mem[Rs+Rt]=Rd 4.15.1 [20] What must be changed in the pipelined datapath to add this
Exercise 4.14 In this exercise, we examine how resource hazards, control hazards, and ISA design can affect pipelined execution. Problems in this exercise refer to the following fragment of MIPS code:Instruction sequencea. lw $1,40($6)beq $2,$0,Label ; Assume $2 == $0 sw $6,50($2)Label: add
Exercise 4.13 In this exercise, we examine how data dependences affect execution in the basic fi ve-stage pipeline described in Section 4.5. Problems in this exercise refer to the following sequence of instructions:Instruction sequencea. lw $1,40($6)add $6,$2,$2 sw $6,50($1)b. lw $5,–16($5)sw
Exercise 4.12 In this exercise, we examine how pipelining affects the clock cycle time of the processor. Problems in this exercise assume that individual stages of the datapath have the following latencies:IF ID EX MEM WBa. 300ps 400ps 350ps 500ps 100psb. 200ps 150ps 120ps 190ps 140ps 4.12.1 [5]
Exercise 4.11 In this exercise we examine in detail how an instruction is executed in a single-cycle datapath. Problems in this exercise refer to a clock cycle in which the processor fetches the following instruction word:Instruction worda. 10001100010000110000000000010000b.
Exercise 4.10 In this exercise we examine how the clock cycle time of the processor affects the design of the control unit, and vice versa. Problems in this exercise assume that the logic blocks used to implement the datapath have the following latencies:I-Mem Add Mux ALU Regs D-Mem Sign-extend
Exercise 4.9 In this exercise we examine the operation of the single-cycle datapath for a particular instruction. Problems in this exercise refer to the following MIPS instruction:Instructiona. lw $1,40($6)b. Label: bne $1,$2,Label 4.9.1 [10] What is the value of the instruction word?4.9.2 [10]
Exercise 4.8 When silicon chips are fabricated, defects in materials (e.g., silicon) and manufacturing errors can result in defective circuits. A very common defect is for one wire to affect the signal in another. This is called a cross-talk fault. A special class of cross-talk faults is when a
Exercise 4.7 In this exercise we examine how latencies of individual components of the datapath affect the clock cycle time of the entire datapath, and how these components are utilized by instructions. For problems in this exercise, assume the following latencies for logic blocks in the
Exercise 4.6 Problems in this exercise assume that logic blocks needed to implement a processor’s datapath have the following latencies:I-Mem Add Mux ALU Regs D-Mem Sign-extend Shift-left-2a. 400ps 100ps 30ps 120ps 200ps 350ps 20ps 2psb. 500ps 150ps 100ps 180ps 220ps 1000ps 90ps 20ps 4.6.1 [10]
Exercise 4.5 The goal of this exercise is to help you familiarize yourself with the design and operation of sequential logical circuits. Problems in this exercise refer to this ALU operation:ALU operationa. Add-one (X+1)b. Shift left by 2 bits (X
Exercise 4.4 When implementing a logic expression in digital logic, one must use the available logic gates to implement an operator for which a gate is not available. Problems in this exercise refer to the following logic expressions:Control signal 1 Control signal 2a. (((A OR B) OR C) OR(A AND C))
Exercise 4.4 When implementing a logic expression in digital logic, one must use the available logic gates to implement an operator for which a gate is not available. Problems in this exercise refer to the following logic expressions:Control signal 1 Control signal 2a. (((A OR B) OR C) OR(A AND C))
Exercise 4.3 Problems in this exercise refer to the following logic block:Logic Blocka. Small I-Memory with four 8-bit wordsb. Small Registers unit with two 8-bit registers 4.3.1 [5] Does this block contain logic only, fl ip-fl ops only, or both?4.3.2 [20] Show how this block can be implemented.
Exercise 4.2 The basic single-cycle MIPS implementation in Figure 4.2 can only implement some instructions. New instructions can be added to an existing ISA, but the decision whether or not to do that depends, among other things, on the cost and complexity such an addition introduces into the
Exercise 4.1 Different instructions utilize different hardware blocks in the basic single-cycle implementation. The next three problems in this exercise refer to the following instruction:Instruction Interpretationa. add Rd,Rs,Rt Reg[Rd]=Reg[Rs]+Reg[Rt]b. lw Rt,Offs(Rs)
Exercise 3.15 Binary numbers are used in the mantissa fi eld, but they do not have to be. IBM used base 16 numbers, for example, in some of their fl oating-point formats. There are other approaches that are possible as well, each with their own particular advantages and disadvantages. The following
Exercise 3.14 The associative law is not the only one that does not always hold in dealing with fl oating-point numbers. There are other oddities that occur as well. The following table shows sets of decimal numbers.A B Ca. 1.5234375 x 10–1 2.0703125 x 10–1 9.96875 x 101b. –2.7890625 x 101

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Computer Organization And Design The Hardware Software Interface 4th Edition David A. Patterson, John L. Hennessy - Solutions

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