Exercise 2.35 The ARM processor has a few different addressing modes that are not supported in MIPS. The following problems explore these new addressing modes.

a. LDR r0, [r1] ; r0 = memory[r1]

b. LDMIA r0, {r1, r2, r4} ; r1 = memory[r0], r2 = memory[r0+4]

; r4 = memory[r0+8]

2.35.1 [5] <2.16> Identify the type of addressing mode of the ARM assembly instructions in the table above.
2.35.2 [5] <2.16> For the ARM assembly instructions above, write a sequence of MIPS assembly instructions to accomplish the same data transfer.
In the following problems, you will compare code written using the ARM and MIPS instruction sets. The following table shows code written in the ARM instruction set.

a. LDR r0, =Table1 ;load base address of table LDR r1, #100 ;initialize loop counter EOR r2, r2, r2 ;clear r2 ADDLP: LDR r4, [r0] ;get fi rst addition operand ADD r2, r2, r4 ;add to r2 ADD r0, r0, #4 ;increment to next table element SUBS r1, r1, #1 ;decrement loop counter BNE ADDLP ;if loop counter != 0, go to ADDLP

b. ROR r1, r2, #4 ;r1 = r23:0 concatenated with r231:4 2.35.3 [10] <2.16> For the ARM assembly code above, write an equivalent MIPS assembly code routine.
2.35.4 [5] <2.16> What is the total number of ARM assembly instructions required to execute the code? What is the total number of MIPS assembly instructions required to execute the code?
2.35.5 [5] <2.16> Assuming that the average CPI of the MIPS assembly routine is the same as the average CPI of the ARM assembly routine, and the MIPS processor has an operation frequency that is 1.5 times the ARM processor, how much faster is the ARM processor than the MIPS processor?