Exercise 2.38 The x86 instruction set includes the REP prefi x that causes the instruction to be repeated a given number of times or until a condition is satisfi ed. The fi rst three problems in this exercise refer to the following x86 instruction:

Instruction Interpretation

a. REP MOVSB Repeat until ECX is zero:

Mem8[EDI]=Mem8[ESI], EDI=EDI+1, ESI=ESI+1, ECX=ECX–1

b. REP MOVSD Repeat until ECX is zero:

Mem32[EDI]=Mem32[ESI], EDI=EDI+4, ESI=ESI+4, ECX=ECX–1 2.38.1 [5] <2.17> What would be a typical use for this instruction?

2.38.2 [5] <2.17> Write MIPS code that performs the same operation, assuming that $a0 corresponds to ECX, $a1 to EDI, $a2 to ESI, and $a3 to EAX.

2.38.3 [5] <2.17> If the x86 instruction takes one cycle to read memory, one cycle to write memory, and one cycle for each register update, and if MIPS takes one cycle per instruction, what is the speed-up of using this x86 instruction instead of the equivalent MIPS code when ECX is very large? Assume that the clock cycle time for x86 and MIPS is the same.

The remaining three problems in this exercise refer to the following function, given in both C and x86 assembly. For each x86 instruction, we also show its length in the x86 variable-length instruction format and the interpretation (what the instruction does). Note that the x86 architecture has very few registers compared to MIPS, and as a result the x86 calling convention is to push all arguments onto the stack. The return value of an x86 function is passed back to the caller in the EAX register.

C code x86 code

a. int f(int

a, int b){

return a+b;

}

f: push %ebp ; 1B, push %ebp to stack mov %esp,%ebp ; 2B, move %esp to %ebp mov 0xc(%ebp),%eax ; 3B, load 2nd arg to %eax add 0x8(%ebp),%eax ; 3B, add 1st arg to %eax pop %ebp ; 1B, restore %ebp ret ; 1B, return

b. void f(int *a, int *b){

*a=*a+*b;

*b=*a;

}

f: push %ebp ; 1B, push %ebp to stack mov %esp,%ebp ; 2B, move %esp to %ebp mov 8(%ebp),%eax ; 3B, load 1st arg into %eax mov 12(%ebp),%ecx ; 3B, load 2nd arg into %ecx mov (%eax),%edx ; 2B, load *a into %edx add (%ecx),%edx ; 2B, add *b to %edx mov %edx,(%eax) ; 2B, store %edx to *a mov %edx,(%ecx) ; 2B, store %edx to *b pop %ebp ; 1B, restore %ebp ret ; 1B, return 2.38.4 [5] <2.17> Translate this function into MIPS assembly. Compare the size (how many bytes of instruction memory are needed) for this x86 code and for your MIPS code.
2.38.5 [5] <2.17> If the processor can execute two instructions per cycle, it must at least be able to read two consecutive instructions in each cycle. Explain how it would be done in MIPS and how it would be done in x86.
2.38.6 [5] <2.17> If each MIPS instruction takes one cycle, and if each x86 instruction takes one cycle plus a cycle for each memory read or write it has to perform, what is the speed-up of using x86 instead of MIPS? Assume that the clock cycle time is the same in both x86 and MIPS, and that the execution takes the shortest possible path through the function (i.e., every loop is exited immediately and every if statement takes the direction that leads toward the return from the function). Note that x86 ret instruction reads the return address from the stack.