Exercise 4.10 In this exercise we examine how the clock cycle time of the processor affects the design of the control unit, and vice versa. Problems in this exercise assume that the logic blocks used to implement the datapath have the following latencies:

I-Mem Add Mux ALU Regs D-Mem Sign-extend Shift-left-2 ALU Ctrl

a. 400ps 100ps 30ps 120ps 200ps 350ps 20ps 0ps 50ps

b. 500ps 150ps 100ps 180ps 220ps 1000ps 90ps 20ps 55ps 4.10.1 [10] <4.2, 4.4> To avoid lengthening the critical path of the datapath shown in Figure 4.24, how much time can the control unit take to generate the MemWrite signal.

4.10.2 [20] <4.2, 4.4> Which control signal in Figure 4.24 has the most slack and how much time does the control unit have to generate it if it wants to avoid being on the critical path?

4.10.3 [20] <4.2, 4.4> Which control signal in Figure 4.24 is the most critical to generate quickly and how much time does the control unit have to generate it if it wants to avoid being on the critical path?

The remaining problems in this exercise assume that the time needed by the control unit to generate individual control signals is as follows:

RegDst Jump Branch MemRead MemtoReg ALUOp MemWrite ALUSrc RegWrite

a. 720ps 730ps 600ps 400ps 700ps 200ps 710ps 200ps 800ps

b. 1600ps 1600ps 1400ps 500ps 1400ps 400ps 1500ps 400ps 1700ps 4.10.4 [20] <4.4> What is the clock cycle time of the processor?

4.10.5 [20] <4.4> If you can speed up the generation of control signals, but the cost of the entire processor increases by $1 for each 5ps improvement of a single control signal, which control signals would you speed up and by how much to maximize performance? What is the cost (per processor) of this performance improvement?

4.10.6 [30] <4.4> If the processor is already too expensive, instead of paying to speed it up as we did in 4.10.5, we want to minimize its cost without further slowing it down. If you can use slower logic to implement control signals, saving $1 of the processor cost for each 5ps you add to the latency of a single control signal, which control signals would you slow down and by how much to reduce the processor’s cost without slowing it down?