Exercise 4.30 In this exercise, we make several assumptions. First, we assume that an N-issue superscalar processor can execute any N instructions in the same cycle, regardless of their types. Second, we assume that every instruction is independently chosen, without regard for the instruction that precedes or follows it. Third, we assume that there are no stalls due to data dependences, that no delay slots are used, and that branches execute in the EX stage of the pipeline. Finally, we assume that instructions executed in the program are distributed as follows:

ALU Correctly predicted beq Incorrectly predicted beq lw sw

a. 50% 18% 2% 20% 10%

b. 40% 10% 5% 35% 10%

4.30.1 [5] <4.10> What is the CPI achieved by a 2-issue static superscalar processor on this program?

4.30.2 [10] <4.10> In a 2-issue static superscalar whose predictor can only handle one branch per cycle, what speed-up is achieved by adding the ability to predict two branches per cycle? Assume a stall-on-branch policy for branches that the predictor can not handle.

4.30.3 [10] <4.10> In a 2-issue static superscalar processor that only has one register write port, what speed-up is achieved by adding a second register write port?

4.30.4 [5] <4.10> For a 2-issue static superscalar processor with a classic fi ve-stage pipeline, what speed-up is achieved by making the branch prediction perfect?

4.30.5 [10] <4.10> Repeat Exercise 4.30.4, but for a 4-issue processor. What conclusion can you draw about the importance of good branch prediction when the issue width of the processor is increased?

4.30.6 <4.10> Repeat Exercise 4.30.5, but now assume that the 4-issue processor has 50 pipeline stages. Assume that each of the original fi ve stages is broken into ten new stages, and that branches are executed in the fi rst of ten new EX stages.
What conclusion can you draw about the importance of good branch prediction when the pipeline depth of the processor is increased?