Question: Exercise 4.32 Problems in this exercise assume that branches represent the following fraction of all executed instructions, and the following branch predictor accuracy. Assume that

Exercise 4.32 Problems in this exercise assume that branches represent the following fraction of all executed instructions, and the following branch predictor accuracy. Assume that the processor is never stalled by data and resource dependences, i.e., the processor always fetches and executes the maximum number of instructions per cycle if there are no control hazards. For control dependences, the processor uses branch prediction and continues fetching from the predicted path. If the branch has been mispredicted, when the branch outcome is resolved the instructions fetched after the mispredicted branch are discarded, and in the next cycle the processor starts fetching from the correct path.

Branches as a % of all executed instructions Branch prediction accuracy

a. 20 90%

b. 20 99.5%

4.32.1 [5] <4.11> How many instructions are expected to be executed between the time one branch misprediction is detected and the time the next branch misprediction is detected?

The remaining problems in this exercise assume the following pipeline depth and that the branch outcome is determined in the following pipeline stage (counting from stage 1):
Pipeline depth Branch outcome known in stage

a. 12 10

b. 25 18 4.32.2 [5] <4.11> In a 4-issue processor with these pipeline parameters, how many branch instructions can be expected to be “in progress” (already fetched but not yet committed) at any given time?
4.32.3 [5] <4.11> How many instructions are fetched from the wrong path for each branch misprediction in a 4-issue processor?
4.32.4 [10] <4.11> What is the speed-up achieved by changing the processor from 4-issue to 8-issue? Assume that the 8-issue and the 4-issue processor differ only in the number of instructions per cycle, and are otherwise identical (pipeline depth, branch resolution stage, etc.).
4.32.5 [10] <4.11> What is the speed-up of executing branches 1 stage earlier in a 4-issue processor?
4.32.6 [10] <4.11> What is the speed-up of executing branches 1 stage earlier in a 8-issue processor? Discuss the difference between this result and the result from Exercise 4.32.5.

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