Exercise 4.6 Problems in this exercise assume that logic blocks needed to implement a processor’s datapath have the following latencies:

I-Mem Add Mux ALU Regs D-Mem Sign-extend Shift-left-2

a. 400ps 100ps 30ps 120ps 200ps 350ps 20ps 2ps

b. 500ps 150ps 100ps 180ps 220ps 1000ps 90ps 20ps 4.6.1 [10] <4.3> If the only thing we need to do in a processor is fetch consecutive instructions (Figure 4.6), what would the cycle time be?

4.6.2 [10] <4.3> Consider a datapath similar to the one in Figure 4.11, but for a processor that only has one type of instruction: unconditional PC-relative branch.

What would the cycle time be for this datapath?

4.6.3 [10] <4.3> Repeat Exercise 4.6.2, but this time we need to support only conditional PC-relative branches.

The remaining three problems in this exercise refer to the following logic block

(resource) in the datapath:

Resource

a. Add 4 (to the PC)

b. Data Memory 4.6.4 [10] <4.3> Which kinds of instructions require this resource?

4.6.5 [20] <4.3> For which kinds of instructions (if any) is this resource on the critical path?

4.6.6 [10] <4.3> Assuming that we only support beq and add instructions, discuss how changes in the given latency of this resource affect the cycle time of the processor. Assume that the latencies of other resources do not change.