Exercise 5.11 In this exercise, we will examine space/time optimizations for page tables. The following table shows parameters of a virtual memory system.

Virtual address (bits) Physical DRAM installed Page size PTE size (byte)

a. 32 4 GB 8 KB 4

b. 64 16 GB 4 KB 8 5.11.1 [10] <5.4> For a single-level page table, how many page table entries (PTE)

are needed? How much physical memory is needed for storing the page table?

5.11.2 [10] <5.4> Using a multilevel page table can reduce the physical memory consumption of page tables by only keeping active PTEs in physical memory. How many levels of page tables will be needed in this case? And how many memory references are needed for address translation if missing in TLB?

5.11.3 [15] <5.4> An inverted page table can be used to further optimize space and time. How many PTEs are needed to store the page table? Assuming a hash table implementation, what are the common-case and worse-case numbers of memory references needed for servicing a TLB miss?

The following table shows the contents of a four-entry TLB.

Entry-ID Valid VA page Modifi ed Protection PA page 1 1 140 1 RW 30 2 0 40 0 RX 34 3 1 200 1 RO 32 4 1 280 0 RW 31 5.11.4 [5] <5.4> Under what scenarios would entry 2’s valid bit be set to 0?
5.11.5 [5] <5.4> What happens when an instruction writes to VA page 30? When would a software-managed TLB be faster than a hardware-managed TLB?
5.11.6 [5] <5.4> What happens when an instruction writes to VA page xxx?