Exercise 5.4 For a direct-mapped cache design with 32-bit address, the following bits of the address are used to access the cache.

Tag Index Offset

a. 31–10 9–4 3–0

b. 31–12 11–15 4–0 5.4.1 [5] <5.2> What is the cache line size (in words)?

5.4.2 [5] <5.2> How many entries does the cache have?

5.4.3 [5] <5.2> What is the ratio between total bits required for such a cache implementation over the data storage bits?

Starting from power on, the following byte-addressed cache references are recorded.

Address 0 4 16 132 232 160 1024 30 140 3100 180 2180 5.4.4 [10] <5.2> How many blocks are replaced?

5.4.5 [10] <5.2> What is the hit ratio?

5.4.6 [20] <5.2> List the fi nal state of the cache, with each valid entry represented as a record of .