Exercise 6.10 Section 6.6 defi nes an eight-step process for handling interrupts. The Cause and Status registers together provide information on the cause of the interrupt and the status of the interrupt handling system. Explore interrupt handling by answering the questions about the following combinations of interrupts.

a. Power Down Overheat Ethernet Controller Data

b. Overheat Reboot Mouse Controller 6.10.1 [5] <6.6> When an interrupt is detected, the Status register is saved and all but the highest priority interrupt is disabled. Why are low-priority interrupts disabled? Why is the Status register saved prior to disabling interrupts?

6.10.2 [10] <6.6> Prioritize interrupts from the devices listed in each table row.

6.10.3 [10] <6.6> Outline how an interrupt from each of the devices listed in the table would be handled.

6.10.4 [5] <6.6> What happens if the interrupt enable bit of the Cause register is not set when handling an interrupt? What value could the interrupt mask value take to accomplish the same thing?
6.10.5 [5] <6.6> Most interrupt-handling systems are implemented in the operating system. What hardware support could be added to make interrupt handling more effi cient? Contrast your solution to potential hardware support for function calls.
6.10.6 [5] <6.6> In some interrupt-handling implementations, an interrupt causes an immediate jump to an interrupt vector. Instead of a Cause register where each interrupt sets a bit, each interrupt has its own interrupt vector. Can the same priority interrupt system be implemented using this approach? Is there any advantage to this approach?