Control hazards can be eliminated by adding branch delay slots. How many delay slots must follow each branch if we want to eliminate all control hazards in this processor?

This exercise is intended to help you better understand the relationship between ISA design and pipelining. Problems in this exercise assume that we have a multiple issue pipelined processor with the following number of pipeline stages, instructions issued per cycle, stage in which branch outcomes are resolved, and branch predictor accuracy:

Transcribed Image Text:

a. b. Pipeline Issue Width Depth 15 25 2 4 Branches Execute in Stage 10 15 Branch Predictor Accuracy 90% 96% Branches as a % of Instructions 25% 15%