How many iterations of your loop from 4.35.4 can be “in light” within this processor’s pipeline? We say that an iteration is “in light” when at least one of its instructions has been fetched and has not yet been committed.

Exercise 4.35.4

ranslate this C loop into MIPS instructions, assuming that our ISA requires one delay slot for every branch. Try to ill delay slots with non-NOP instructions when possible. You can assume that variables a, b, c, i, and j are kept in registers r1, r2, r3, r4, and r5.

The remaining four problems in this exercise refer to the following C loop:

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a. b. for(i=0;i!-j; i++) { c+=a[i]; } for(i=0;i!-j;i+=2) { c+ a[i]-a[i+1]; }