In vectored exception handling, the table of exception handler addresses is in data memory at a known (fixed) address. Change the pipeline to implement this exception handling mechanism. Repeat 4.25.3 using this modified pipeline and vectored exception handling.

Exercise 4.25.3

If the second instruction from this table is fetched right after the instruction from the first table, describe what happens in the pipeline when the first instruction causes the first exception you listed in 4.25.1. Show the pipeline
execution diagram from the time the first instruction is fetched until the time the first instruction of the exception handler is completed.

Exercise 4.25.1

Which exceptions can each of these instructions trigger? For each of these exceptions, specify the pipeline stage in which it is detected.

The remaining three problems in this exercise assume that exception handlers are located at the following addresses:

Transcribed Image Text:

Overflow a. 0x1000CB05 b. 0x450064E8 Invalid Data Address Ox1000D230 OXC8203E20 Undefined Invalid Instruction Instruction Address Ox1000D780 OXC8203E20 Ox1000E230 0x678A0000 Hardware Malfunction 00x1000F254 0x00000010