Question: The x86 instruction set includes the REP prefix that causes the instruction to be repeated a given number of times or until a condition is
The x86 instruction set includes the REP prefix that causes the instruction to be repeated a given number of times or until a condition is satisfied. Note that x86 instructions refer to 8 bits as a byte, 16 bits as a word, and 32 bits as a double word. The first three problems in this Exercise refer to the following x86 instruction:![Instruction a. REP MOVSW b. REPNE SCASB Interpretation Repeat until ECX is zero: Mem16[EDI]=Mem16[ESI].](https://dsd5zvtm8ll6.cloudfront.net/images/question_images/1698/1/4/1/9656537970d98ec11698141964405.jpg)
If the x86 instruction takes one cycle to read memory, one cycle to write memory, and one cycle for each register update, and if MIPS takes one cycle per instruction, what is the speedup of using this x86 instruction instead of the equivalent MIPS code when ECX is very large? Assume that the clock cycle time for x86 and MIPS is the same.
Instruction a. REP MOVSW b. REPNE SCASB Interpretation Repeat until ECX is zero: Mem16[EDI]=Mem16[ESI]. EDI-EDI+2, ESI-ESI+2, ECX-ECX-1 Repeat until ECX is zero: If Mem8[EDI] AL then go to next instruction, otherwise EDI-EDI+1, ECX-ECI+1. Note: AL is the least- significant byte of the EAX register.
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It seems the image youve provided indicates that there are two instructions REP MOVSW and REPNZ or REPNE SCASB each with specific operations as define... View full answer
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