The bus controlled by the parallel arbitration logic shown in Fig. 13-11 is initially idle. Devices 2 and 3 then request the bus at the same time. Specify the input and output binary values in the encoder and decoder and determine which bus arbiter is acknowledged.

Fig. 13-11

Bus arbiter 1 Ack Req Bus arbiter 2 Ack Req 4X2 Priority encoder 2X4 Decoder Bus arbiter 3 Ack Req Bus arbiter 4 Ack Req Bus busy line