What has to be done to the bus system of Fig. 4-3 to be able to transfer information from any register to any other register? Specifically, show the connections that must be included to provide a path from the outputs of register C to the inputs of register A.

Fig. 4-3

Transcribed Image Text:

S₁ So 4x1 MUX 3 3 2 1 0 D₂ D₁ Do 3 2 10 Register D 4x1 MUX 2 32 10 D2 C2 B2 A2 C₂ C₁ Co 3210 Register C 4x1 MUX 1 3 2 10 D₁ C₁ B₁ A₁ Bi Bi Bo 3210 Register B 4x1 MUX 0 4- line common bus 3 2 1 0 Do Co Bo Áo A2 A₁ Ao 32 10 Register A