The register signal srcB indicates which register should be read to generate the signal valB. The desired value is shown as the second step in the decode stage in Figures 4.18 to 4.21. Write HCL code for srcB.

Figures 4.18

Figures 4.21

Stage Fetch Decode Execute Memory Write back PC update OPq rA, rB icode: ifun rA:B M [PC] M [PC + 1] valp - PC+2 valA - R[rA] valB R[TB] valEvalB OP valA Set CC R[rB] valE PC - valP rrmov rA, rB icode:ifun M[PC] rA:rB M[PC + 1] valp PC+2 valA - R[rA] valE - R[RB] 0 + valA valE PC - valP irmovq V, rB icode: ifun - M[PC] rA:rB M[PC + 1] valc Mg[PC + 2] valp PC + 10 valE + 0 + valC R[TB] PC valE valp