Questions and Answers of Computer Systems A Programmers Perspective

In the previous dotprod example, what fraction of the total references to x and y will be hits once we have padded array x?Example:For example, instead of defining x to be float x[8], we define it to
Consider the following declarations:Fill in the following table describing the element size, the total size, and the address of element i for each of these arrays.
Suppose you are given the job of checking that a C compiler generates the proper code for structure and union access. You write the following structure declaration:with different access expressions
The following C code sets the diagonal elements of one of our fixed-size arrays to val:When compiled with optimization level -01, GCC generates the following assembly code:Create a C code program
Use Equation 3.1 to explain how the computations of the initial values for Aptr, Bptr, and Bend in the C code of Figure 3.37(b) correctly describe their computations in the assembly code generated
Consider the following source code, where M and N are constants declared with #define:In compiling this program, gcc generates the following assembly code:Use your reverse engineering skills to
Suppose xP, the address of short integer array P, and long integer index i are stored in registers %rdx and %rcx, respectively. For each of the following expressions, give its type, a formula for its
For a C function having the general structureA. What value does rfun store in the callee-saved register %rbx?B. Fill in the missing expressions in the C code shown above. long rfun (unsigned long x)
Consider a function P, which generates local values, named a0–a8. It then calls function Q using these generated values as arguments. Gcc produces the following code for the first part of P:A.
A C function procprob has four arguments u, a, v, and b. Each is either a signed number or a pointer to a signed number, where the numbers have different sizes. The function has the following
The disassembled code for two functions first and last is shown below, along with the code for a call of first by function main:Each of these instructions is given a label, similar to those in Figure
For a C function switcher with the general structuregcc generates the assembly code and jump table shown in Figure 3.24.Fill in the missing parts of the C code. Except for the ordering of case labels
Starting with C code of the form short test (short x, short y) { short val = if ( if ( else .L2: val = ) { } else if ( val = return val; movq imulq movq orq cmpq cmovge ret val = } GCC generates the
A. Try to calculate 14! with a 32-bit int. Verify whether the computation of 14! overflows.B. What if the computation is done with a 64-bit long int?
A. Which registers are used to hold program values x, y, and n?B. How has the compiler eliminated the need for pointer variable p and the pointer dereferencing implied by the expression (*p)+=5?C.
We can see that the compiler used a jump-to-middle translation, using the jmp instruction on line 3 to jump to the test starting with label .L2. Fill in the missing parts of the C code. For C code
Figure 3.21 C and assembly code for while version of factorial using guarded-do translation. The fact_while_gd_goto function illustrates the operation of the assembly-code version.We can see that
A function test_one has the following overall structure:Reverse engineer the operation of this code and then do the following:A. Determine what loop translation method was used.B. Use the
Write goto code for a function called fibonacci to print fibonacci numbers using a while loop. Apply the guarded-do transformation.
A function test_two has the following overall structure:Reverse engineer the operation of this code and then do the following:A. Use the assembly-code version to fill in the missing parts of the C
Executing a continue statement in C causes the program to jump to the end of the current loop iteration. The stated rule for translating a for loop into a while loop needs some refinement when
In the C function that follows, we have omitted the body of the switch statement. In the C code, the case labels did not span a contiguous range, and some cases had multiple labels.In compiling the
In the following C function, we have left the definition of operation 0P incomplete:A. What operation is 0P?B. Annotate the code to explain how it works. #define OP short arith (short x) { return x
Running on a new processor model, our code required around 45 cycles when the branching pattern was random, and around 25 cycles when the pattern was highly predictable.A. What is the approximate
Starting with C code of the form short test (short x, short y, short z) { short val = ) { if C cmpq jle capq jle .L3: } GCC generates the following assembly code: short test (short x, short y, short
An alternate rule for translating if statements into goto code is as follows:A. Rewrite the goto version of absdiff_se based on this alternate rule.B. Can you think of any reasons for choosing one
A. Write a goto version in C that performs the same computation and mimics the control flow of the assembly code, in the style shown in Figure 3.16(b). You might find it helpful to first annotate the
In the following excerpts from a disassembled binary, some of the information has been replaced by X’s. Answer the following questions about these instructions.A. What is the target of the je
Shows a general comparison between argument a and 0, where we can set the data type of the argument by declaring data_t with a typedef, and the nature of the comparison by declaring TEST with a
Shows a general comparison between arguments a and b, where data_t, the data type of the arguments, is defined (via typedef) to be one of the integer data types listed in Figure 3.1 and either signed
Consider the following function for computing the quotient and remainder of two unsigned 64-bit numbers: void uremdiv(unsigned long x, unsigned long y, unsigned long *qp, unsigned long *rp)
It is common to find assembly-code lines of the formxorq %rcx, %rcxIn code that was generated from C where no exclusive-or operations were present.A. Explain the effect of this particular
Consider the following code, in which we have omitted the expression being computed: short arith3 (short x, short y, short z) { } short p1. short p2 short p3 = short p4 = return p4; The portion of
Suppose we want to generate assembly code for the following C function:The code that follows is a portion of the assembly code that performs the actual shifts and leaves the final value in register
Assume the following values are stored at the indicated memory addresses and registers:Fill in the following table showing the effects of the following instructions, in terms of both the register or
Consider the following code, in which we have omitted the expression being computed: short scale3 (short x, short y, short z) { short t = return t; } Compiling the actual function with GCC yields the
Suppose register %rbx holds value p and %rdx holds value q. Fill in the table below with formulas indicating the value that will be stored in register %rax for each of the given assembly-code
You are given the following information. A function with prototypevoid decode1(long *xp, long *yp, long *zp);Is compiled into assembly code, yielding the following:Parameters xp, yp, and zp are
Assume variables sp and dp are declared with typeswhere src_t and dest_t are data types declared with typedef. We wish to use the appropriate pair of data movement instructions to implement the
Each of the following lines of code generates an error message when we invoke he assembler. Explain what is wrong with each line. movb $0xF, (%ebx) movl %rax, (%rsp) movw (%rax), 4 (%rsp) movb %al,
For each of the following lines of assembly language, determine the appropriate instruction suffix based on the operands. (For example, mov can be rewritten as movb, movw, movl, or movq.)
Assume the following values are stored at the indicated memory addresses and registers:Fill in the following table showing the values for the indicated operands: Address Value 0x100 OXFF 0x104
Assume variables x, f, and d are of type int, float, and double, respectively. Their values are arbitrary, except that neither f nor d equals +∞, −∞, or NaN. For each of the following C
Fill in the following macro definitions to generate the double-precision values +∞, −∞, and −0:You cannot use any include files (such as math.h), but you can make use of the fact that the
Consider the following two 7-bit floating-point representations based on the IEEE floating-point format. Neither has a sign bit—they can only represent nonnegative numbers.1. Format AThere are k =
Show how the following binary fractional values would be rounded to the nearest half (1 bit to the right of the binary point), according to the round-to-even rule. In each case, show the numeric
Armed with the function inplace_swap from Problem 2.10, you decide to write code that will reverse the elements of an array by swapping elements from opposite ends of the array, working toward the
The Patriot missile software approximated 0.1 as x = 0.000110011001100110011002. Suppose instead that they had used IEEE round-to-even mode to determine an approximation x' to 0.1 with 23 bits to the
As we will see in Chapter 3, the LEA instruction can perform computations of the form (a
Fill in the following table showing the results of multiplying different 3-bit numbers, in the style of Figure 2.27:Figure 2.27 Mode Unsigned Two's complement Unsigned Two's complement Unsigned Two's
Explain how Equation 2.5 applies to the entries in the table you generated when solving Problem 2.19.Eq. 2.5
Consider the following structure declaration:This declaration illustrates that one structure can be embedded within another, just as arrays can be embedded within structures and arrays can be
The following code shows the declaration of a structure of type ACE and the prototype for a function test:A. Use your reverse engineering skills to write C code for test.B. Describe the data
For each of the following structure declarations, determine the offset of each field, the total size of the structure, and its alignment requirement for x86-64: A. struct P1 { short i; int c; int *j;
Answer the following for the structure declarationA. What are the byte offsets of all the fields in the structure?B. What is the total size of the structure?C. Rearrange the fields of the structure
Figure 3.41 shows a (low-quality) implementation of a function that reads a line from standard input, copies the string to newly allocated storage, and returns a pointer to the result. Consider the
Running our stack-checking code 10,000 times on a system running Linux version 2.6.16, we obtained addresses ranging from a minimum of 0xffffb754 to a maximum of 0xffffd754.A. What is the approximate
Suppose you work as a truck driver, and you have been hired to carry a load of potatoes from Boise, Idaho, to Minneapolis, Minnesota, a total distance of 2,500 kilometers. You estimate you can
The functions intlen, len, and iptoa provide a very convoluted way to compute the number of decimal digits required to represent an integer. We will use this as a way to study some aspects of the gcc
In this problem, we will explore the logic behind the code in lines 5-11 of Figure 3.43(b), where space is allocated for variable-size array p. As the annotations of the code indicate, let us let s1
For the following C code, the expressions val1–val4 all map to the program values i, f, d, and l: double fcvt2(int *ip, float *fp, double *dp, long 1) { } 1 2 3 4 5 6 7 8 9 10 11 12 int i = *ip;
The following C function converts an argument of type src_t to a return value of type dst_t, where these two types are defined using typedef:For execution on x86-64, assume that argument x is either
Consider the following C function, where EXPR is a macro defined with #define:Below, we show the AVX2 code generated for different definitions of EXPR, where value x is held in %xmm0. All of them
Suppose you want to implement a word-level equality circuit using the EXCLUSIVE-OR circuits from Problem 4.9 rather than from bit-level equality circuits. Design such a circuit for a 64-bit word
What would be the effect of the instruction pushq %rsp according to the steps listed in Figure 4.20? Does this conform to the desired behavior for Y86-64, as determined in Problem 4.7?Problem 4.7Let
Assume the two register writes in the write-back stage for popq occur in the order listed in Figure 4.20.What would be the effect of executing popq %rsp? Does this conform to the desired behavior for
We can see by the instruction encodings (Figures 4.2 and 4.3) that the rrmovq instruction is the unconditional version of a more general class of instructions that include the conditional moves. Show
Suppose a program running on the machine in Problem 6.12 references the 1-byte word at address 0x0D53. Indicate the cache entry accessed and the cache byte value returned in hexadecimal notation.
Repeat Problem 6.13 for memory address 0x0CB4.A. Address format (1 bit per box):B. Memory reference:Problem 6.13Suppose a program running on the machine in Problem 6.12 references the 1-byte word at
Repeat Problem 6.13 for memory address 0x0A31.A. Address format (1 bit per box):B. Memory reference:Problem 6.13Suppose a program running on the machine in Problem 6.12 references the 1-byte word at
For the cache in Problem 6.12, list all of the hexadecimal memory addresses that will hit in set 3.Problem 6.12The problems that follow will help reinforce your understanding of how caches work.
Fill in the right-hand column of the following table to describe the processing of the call instruction on line 9 of the object code in Figure 4.17:Figure 4.17
Write HCL code for the signal need_valC in the SEQ implementation.
The register signal srcB indicates which register should be read to generate the signal valB. The desired value is shown as the second step in the decode stage in Figures 4.18 to 4.21. Write HCL code
Only the popq instruction uses both register file write ports simultaneously. For the instruction popq %rsp, the same address will be used for both the E and M write ports, but with different data.
The conditional move instructions, abbreviated cmovXX, have instruction code IRRMOVQ. As Figure 4.28 shows, we can implement these instructions by making use of the Cnd signal, generated in the
Write HCL code for Stat, generating the four status codes SAOK, SADR, SINS, and SHLT (see Figure 4.26).Figure 4.26
Suppose we use a branch prediction strategy that achieves a success rate of 65%, such as backward taken, forward not taken (BTFNT). What would be the impact on CPI, assuming all of the other
Consider the following program:A. What is the output of the child process?B. What is the output of the parent process? 23 2 4 5 6 7 8 9 int main() { } int a = 9; if (Fork () printf("p1: a=%d\n",
For each of the following function declarations, determine the register assignments for the arguments:` A. double g1 (double a, long b, float c, int d); B. double g2 (int a, double *b, float *c, long
For the following C function, the types of the four arguments are defined by typedef:Determine the possible combinations of types of the four arguments (there may be more than one). double funct1
Function funct2 has the following prototype:double funct2(double w, int x, float y, long z);Gcc generates the following code for the function: 1 23 4 5 6 7 8 9 double funct2(double w, int x, float y,
Show how the numbers declared at label .LC3 encode the number 32.0.
The following assembly-code function lets us determine the behavior of the instruction popq %rsp for x86-64:We find this function always returns 0xabcd. What does this imply about the behavior of
Write an HCL expression for a signal xor, equal to the exclusive-or of inputs a and b. What is the relation between the signals xor and eq defined above?
Fill in the right-hand column of the following table to describe the processing of the popq instruction on line 7 of the object code in Figure 4.17.Figure 4.17 Stage Fetch Generic popq
The HCL code given for computing the minimum of three words contains four comparison expressions of the form X
Write HCL code describing a circuit that for word inputs A, B, and C selects the median of the three values. That is, the output equals the word lying between the minimum and maximum of the three
Fill in the right-hand column of the following table to describe the processing of the irmovq instruction on line 4 of the object code in Figure 4.17:Figure 4.17
Register ID dstM indicates the destination register for write port M, where valM, the value read from memory, is stored. This is shown in Figures 4.18 to 4.21 as the second step in the write-back
Based on the first operand of the first step of the execute stage in Figures 4.18 to 4.21, write an HCL description for the signal aluB in SEQ.Figures 4.18Figures 4.21
Looking at the memory operations for the different instructions shown in Figures 4.18 to 4.21, we can see that the data for memory writes are always either valA or valP. Write HCL code for the signal
We want to set the control signal mem_write only for instructions that write data to memory. Write HCL code for the signal mem_write in SEQ.
Suppose the order of the fifth and sixth cases (the two forwarding sources from the write-back stage) in the HCL code for d_valA were reversed. Write a Y86-64 program that would be executed
Let us continue exploring ways to evaluate polynomials, as described in Practice Problem 5.5. We can reduce the number of multiplications in evaluating a polynomial by applying Horner’s method,
Modify the code for combine5 to unroll the loop by a factor k = 5.
Suppose we analyze the combinational logic of Figure 4.32 and determine that it can be separated into a sequence of six blocks, named A to F, having delays of 80, 30, 60, 50, 70, and 10 ps,
Suppose we could take the system of Figure 4.32 and divide it into an arbitrary number of pipeline stages k, each having a delay of 300/k, and with each pipeline register having a delay of 20 ps.A.
Write HCL code for the signal f_stat, providing the provisional status for the fetched instruction.
The block labeled “dstE” in the decode stage generates the register ID for the E port of the register file, based on fields from the fetched instruction in pipeline register D. The resulting

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