Discrete time controlled systems can exhibit unique characteristics not available in continuous controllers. For example, assuming a specific input and some conditions, it is possible to design a system to achieve steady state within one single time sample without overshoot. This scheme is well known and referred to as deadbeat control. We illustrate deadbeat control design with a simple example. For a more comprehensive treatment see (Ogata, 1987).

Assume in Figure 13.25(a) that G_p(s) = 1/s + 1. The purpose of the design will be to find a compensator, G_c(z), such that for a step input the system achieves steady state within one sample. We start by translating the system into the discrete domain to obtain the equivalent of Figure 13.25(c). The pulse transfer function, G_p(z)=(1-e^-T)z^-1/1 - e^-T z^-1 , is found using Eq. (13.40), since it is assumed that the compensator will be followed by a zero-order hold. In Figure 13.25(c), the closed-loop transfer function is given by C(z)/R(z) = T(z) = G_c(z)G_p(z)/1 + G_c(z)G_p(z), or, solving for the compensator, we get G_c(z) = 1/G_p(z) T(z)/1 - T(z). The desired system output is a unit step delayed by one unit sample.

Thus, C(z) = z/z - 1 z^-1 = 1/z - 1. Since the input is a unit step, R(z) = z/z - 1; the desired closed-loop transfer function is C(z)/R(z) = T(z) = z^-1, and the resulting compensator, found by direct substitution, is given by G_c(z) = 1/1 - e^-T (z - e^-T)/z - 1.

Assume now that the plant is given by G_p(s) = 1/s, and a sampling period of T = 0.05 second is used.

a. Design a deadbeat compensator to reach steady state within one time sample for a step input.

b. Calculate the resulting steady-state error for a unit-slope ramp input.

c. Simulate your system using SIMULINK. Show that the system reaches steady state after one sample. Also verify your steady-state error ramp result.