Sketch the state transition diagram for the FSM described by the following HDL code. An FSM of this nature is used in a branch predictor on some microprocessors.?

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SystemVerilog VHDL library IEEE; use IEEE.STD LOGIC_1164. all: module fsm1(input logic clk, reset. input logic taken, back, output logic predicttaken): entity fsml is port(clk, reset: in STD_LOGIC: in STD_LOGIC; predicttaken: out STD LOGIC): logic [4:0] state, nextstate; taken, back: parameter S0 - 5'b00001: parameter SI - 5'b00010: parameter S2 = 5'b00100: parameter $3- 5'b01000: end: architecture synth of fsml is type statetype is (S0, S1, S2, 53. 54): signal state, nextstate: statetype: begin process(clk, reset) begin if reset then state (= S2: elsif rising edge(clk) then state (= nextstate: end if: end process: parameter $4- 5'b10000: always_ff @( posedge clk, posedge reset) if (reset) state (- S2; else state (= nextstate: always_comb case (state) S0: if (taken) nextstate = S1; else nextstate = S0; process (all) begin S1: if (taken) nextstate = S2; else $2: if (taken) nextstate = S3; case state is nextstate = S0; when S0 => if taken then nextstate ( $1: else nextstate (= S0: nextstate- S1: $3: if (taken) nextstate = S4; nextstate = S2; $4: 1f (taken) nextstate = S4; nextstate = S3: else end if: when S1 => if taken then else nextstate > $2: else nextstate (= S0: end if: else default: endcase nextstate = S2: when S2 => 1f taken then assign predicttaken = (state == S4)| (state =- $3) (state == S2 && back): nextstate (= S3: else nextstate (= S1; end if: endmodule when S3 => if taken then nextstate (= $4: else nextstate (= S2: end if: when S4 => if taken then nextstate (= $4; else nextstate (= S3: end if: when others => nextstate (= S2; end case: end process: -- output logic predicttaken (= '1' when ((state = 54) or (state=$3) or (state = S2 and back ='1')) else '0': end: