Assume you have a module that consumes 100 units of area and has a delay of 10
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Assume you have a module that consumes 100 units of area and has a delay of 10 ns. The pipeline registers have an area of 2 units, and treg = 500 ps. By varying the number of pipeline stages, make a graph with throughput on the y-axis and area on the x-axis. What can you say about the cost (area) versus benefit (throughput) for very deep pipelines?
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Related Book For
Digital Design Using VHDL A Systems Approach
ISBN: 9781107098862
1st Edition
Authors: William J. Dally, R. Curtis Harting, Tor M. Aamodt
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