Question: Design a VHDL design entity for receiving periodic (N = 10) eight-bit signals and outputting them to a readyvalid interface. Your module should include the

Design a VHDL design entity for receiving periodic (N = 10) eight-bit signals and outputting them to a ready–valid interface. Your module should include the ability to save up to two of the periodically valid signals if the output is not ready. You may drop the third such packet.

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