Implement a large (32-input) multiplexer in which each multiplexer input and its associated select signal is in a different part of a large chip. The 32 inputs and selects are located along a 0.4 mm long line. Show how this can be implemented using static CMOS gates (e.g., NANDs, NORs, and inverters – no tri-states) with only a single wire running along the line between adjacent input locations.