Question: (a) Implement the traffic-light controller of Figure 4-14 using a module 13 counter with added logic. The counter should increment every clock, with two exceptions.
(a) Implement the traffic-light controller of Figure 4-14 using a module 13 counter with added logic. The counter should increment every clock, with two exceptions. Use a ROM to generate the outputs.
(b) Write a Verilog description of your answer to (a).
(c) Write a test bench for part (b) and verify that your controller works correctly. Use concurrent statements to generate test inputs for Sa and Sb.
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a Clear when Q 3 Q 2 1 CLRN Q 3 Q 2 LOADN 1 Count except in S 5 S b 1 and in S11 S a S b 1 So P T Q ... View full answer
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