(a) Write a Verilog module that describes one bit of a full adder with accumulator. The module should have two control inputs, Ad and L. If Ad = 1, the Y input (and carry input) are added to the accumulator. If L = 1, the Y input is loaded into the accumulator.
(b) Using the module defined in (a), write a Verilog description of a 4-bit subtracter with accumulator. Assume negative numbers are represented in 1’s
complement. The subtracter should have control inputs Su (subtract) and Ld (load).