(a) Write at least two different Verilog modules that are equivalent to the following pseudo code:
A = B1 when C = 1 else B2 when C = 2 else B3 when C = 3 else 0;
(b) Draw a circuit to implement the following statement,
A = B1 when C1 = 1 else B2 when C2 = 1 else B3 when C3 = 1
else 0;