Question: Write a Verilog description of an SR latch. (a) Use a conditional assignment statement (i.e., a behavioral description). (b) Use the characteristic equation in the

Write a Verilog description of an SR latch.
(a) Use a conditional assignment statement (i.e., a behavioral description).
(b) Use the characteristic equation in the Verilog description.
(c) Use the logic gate level structure of an SR latch in the model.

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